Design Of Arithmetic Logic Unit Research Articles

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves

Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization.

Design and implementation of an 8-bit ALU based on verilog HDL

Many modern processors incorporate an Arithmetic Logic Unit (ALU) as an integral component. The ALU plays a pivotal role in arithmetic and logical operations, making it a fundamental block in processor architecture. Utilizing software tools like Quartus II and ModelSim, one can seamlessly design, implement, and simulate an 8-bit ALU. This research focuses on creating an ALU that can perform a broad range of operations, including Addition, Subtraction, Multiplication, Division, Shifting, Rotation, AND, OR, XOR, NOR, NAND, XNOR, and Comparison. With these 16 operations in mind, the ALUs circuitry was meticulously crafted using Quartus II. To validate its functionality and performance, joint simulations were conducted with both Quartus II and ModelSim. As a result, comprehensive simulation waveforms were derived, offering insights into the ALUs behavior and response for each instruction. These waveforms serve as a testament to the ALUs robust design and provide a foundation for further analysis and optimization.

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit.

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer's central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCADesigner-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area.

A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design

Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate, is used for the latest suggested clock gating. This design saves power even when the clock is at applying to the target module. Complete power analysis reveals that the proposed technique has an effect on the dynamic power that decreases total power consumption up to 24.90% relative to traditional power. All experiments are done in arithmetic logic unit design. 130 nm standard logic libraries have been used for implementation in order to achieve ALU frameworks. The ALU design architecture was developed using the Verilog HDL, and the simulations are performed utilizing ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.

Based on FS-GDI Approach with 65 nm Technology: Low Power ALU Design

ABSTRACT This paper presents an area/power efficient design for the Arithmetic Logic Unit (ALU) utilising the FS-GDI approach. The presented ALU is designed in 45 nm, 65 nm and 130 nm node using Cadence Virtuoso simulator. Various ALUI/ALUII designs are presented with different data words. The result of ALUI proves its superiority compared with the traditional CMOS-based design in terms of power consumption, propagation delay and transistor count. The energy of the proposed 4-bit ALU reduced by 32% compared to CMOS based. Scalability of the proposed ALUI and ALUII designs are tested by extending length of the processed bits to 32-bits, through testing the performance of 8-bit, 16-bit, 32-bit ALUs based on the proposed ALUI and ALUII design. It is seen that the energy of the 4-bit ALU reduced by 21.2%, the power efficiency of the DSP and image processing circuits can be improved utilising the proposed designs of the ALUs. The experiment clears the superiority of the proposed ALU units and its suitability for long data words.

Design and Comparative Analysis of High Speed and Low Power ALU Using RCA and Sklansky Adders for High-Performance Systems

This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC design flow, tools used during the flow, and the factors to consider to maximize the performance and power ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part of all processors. In this study, two ALUs were implemented using two different types of adder circuits: a Ripple Carry Adder (RCA) and a Sklansky adder. The Cadence EDA tools were used for the implementation. A comparative analysis was conducted for the two designed ALUs in terms of area, power, and timing analysis. The ALU design was also used as an example to examine the whole workflow front-end wise by constructing a block schematic and back-end wise by floorplanning, placing, and routing the physical design.

Design of an efficient ALU blocks in quantum dot cellular automata (QCA)

Quantum-dot cellular automata (QCA) is a raising nanotechnology with the potential for quicker speed, smaller size and low power consumption than CMOS based technology. This paper proposes the design of functional blocks for Arithmetic Logic Unit (ALU) and for majority gate (MV) using certain unique QCA characteristics. Previous works were based on the conventional design and have different approaches when compared with QCA method. This paper helps to resolve the conventional method by converting all Boolean logics into a NAND and NOR based majority voter by fixing one of the inputs. The proposed work presents a significant amount of reduction in the cell count, area of the cell, and clock delay phase, compared to previous work in QCA. The experimental result shows a reduction in number of cells is by 35.40%, Area of cells (um2) by 15.88% and clock delay phase by 48.21%. Simulations indicate an appealing performance in terms of area, delay, and complexity. Simulation results are validated using the quantum-dot cellular automata (QCA) Designer 2.0.3 tool.

QCA with reversible arithmetic and logic unit for nanoelectronics applications

PurposeIn this research work, brief quantum-dot cellular automata (QCA) concepts are discussed through arithmetic and logic units. This work is most useful for nanoelectronic applications, VLSI industry mainly depends on this type of fault-tolerant QCA based arithmetic logic unit (ALU) design. The ALU design is mainly depending on set instructions and rules; these are maintained through low-power ultra-functional tricks only possible with QCA-based reversible arithmetic and logic unit for nanoelectronics. The main objective of this investigation is to design an ultra-low power and ultra-high-speed ALU design with QCA technology. The following QCA method has been implemented through reversible logic.Design/methodology/approachQCA logic is the main and critical condition for realizing NANO-scale design that delivers considerably fast integrate module, effective performable computation and is less energy efficiency at the nano-scale (QCA). Processors need an ALU in order to process and calculate data. Fault-resistant ALU in QCA technology utilizing reverse logic is the primary objective of this study. There are now two sections, i.e. reversible ALU (RAU), logical (LAU) and arithmetical (RAU).FindingsA reversible 2 × 1 multiplexer based on the Fredkin gate (FRG) was developed to allow users to choose between arithmetic and logical operations. QCA full adders are also implemented to improve arithmetic operations' performance. The ALU is built using reversible logic gates that are fault-tolerant.Originality/valueIn contrast to earlier research, the suggested reversible multilayered ALU with reversible QCA operation is imported. The 8- and 16-bit ALU, as well as logical unit functioning, is designed through fewer gates, constant inputs and outputs. This implementation is designed on the Mentor Graphics QCA tool and verifies all functionalities.

A stable 4-bit ALU design for printed devices

Printed devices fabricated using roll-to-roll (R2R) printing technology have been used in low-cost Internet of Things (IoTs), smart packaging and bio-chips. As the area of applications of printed devices broadens, arithmetic units in digital design need to be implemented. In this paper, we propose a stable 4-bit arithmetic logic unit (ALU) design using a minimum number of transistors that can overcome the limitations of printed devices. We propose the use of a 2:1 transmission gate (TG) multiplexer structure and hybrid 16T full-adder to construct the ALU. New design methods are applied to reduce the number of inverter stages added to overcome the voltage degradation. Using this approach reduces the total number of transistors used in the design from 276 to 153, compared to the conventional design, with significant improvements in delay and power performance.

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM).

Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

Micro-ring resonator based all-optical Arithmetic and Logical Unit

Silicon photonics is achieving developments in optical computing and information processing. It necessitates the efficient design of Arithmetic Logic Unit (ALU) to perform optical micro-operations such as adder/subtractor, comparator. The earlier work reported for ALU design used Mach-Zehnder Interferometer (MZI), semiconductor optical amplifiers, terahertz optical asymmetric demultiplexer (TOAD) and beam splitter. These approaches make optical circuit larger in size and difficult to integrate with Very Large Scale Integrated Optics (VLSIO). Here, we propose an all-optical ALU exclusively using Micro-Ring Resonator (MRR) to perform addition and comparison. The use of MRR to design ALU makes the proposed design novel and easy to integrate with VLSIO. The operations performed are one-bit addition and one-bit comparison. Beam splitter is replaced by MRR which has resulted in low intensity losses. The performance of the proposed ALU is discussed with simulation results and calculated losses. The output is verified for different input combinations of the half adder and comparator with electric field intensity distribution using 1550 nm wavelength. More losses are observed in comparator circuit as compared to adder circuit. Low losses and less MRR makes ALU design optimized.

Design and testing of a reversible ALU by quantum cells automata electro-spin technology

Arithmetic logic unit (ALU), a core component of a processor, is one of the thrust areas of the current research. Presently, ALU is designed by transistor-based CMOS technique and its individual components are placed in different layers. The current design is affected by the limitations of Moore’s law and design complexity. At present, ‘Quantum cellular automata electro-spin (QCA-ES)’ technology is widely accepted technology as an alternative of ‘CMOS’ to minimize the above discussed problems. In this research paper, the design of a novel multilayer portable, dynamic, fault-tolerant, power-efficient, thermally stable reversible ALU is proposed which is explored through QCA-ES. All the arithmetic and logical components of ALU are separately placed in different layers. Area density, delay, fault tolerance and thermal stability are investigated. A specific type of gate, known as reversible gate (modified 3:3 ‘TSG’ gate), is used in this proposed design with QCA technology to get the optimized design ALU with low occupied area, complexity, delay and power dissipation. Investigation of a fault-free design and saturated amplitude level (of output) change with respect to temperature increment in the proposed device are also discussed in this paper. Not only the thermal stability (up to 6 k temperature) but also an investigation on cell complexity of the 100% fault-free (against multiple cell-omission, cell-displacement, cell-orientation change and extra cell deposition), multilayer nano-device is represented in this work. ‘QCA-Designer’ software is used in this research work to design and develop layout of the proposed components in quantum-field and find out the occupied area, delay and complexity of proposed design. ‘QCA-Pro’ software is used for getting the value of dissipated power.

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic

Design of combinational circuits using dynamic logic has the advantage of high speed and less area when compared to conventional CMOS logic. However, it pose problem while cascading dynamic logic architectures and also more prone to leakage current issue. These issues are overcome by using domino logic with static inverter at the output of dynamic node. The increased power dissipation at the output node is reduced by using pseudo dynamic buffer based domino logic by having static like switching at the output node. This paper details the design of arithmetic and logic unit designed using conventional and pseudo dynamic buffer based domino logic. The arithmetic unit comprise adder, subtractor, multiplier and logical unit comprise AND, NAND, OR, NOR and XOR logic blocks based on pseudo dynamic buffer based domino logic and it is compared with the Arithmetic logic unit designed using conventional domino logic. The design and simulations are performed using UMC90nm technology node library using Cadence® Virtuoso® tool. The simulation result of ALU unit demonstrates that arithmetic logic unit designed using PDB logic has reduction in power consumption by 89.14% and delay by 1.995% while compared to conventional domino logic.

Implementation of Quaternary Divider for Performance Optimization

In VLSI technology, designers concentrations is on area required and on performance of the device. In this design power consumption is one of the major concerns due to increase in chip density, continuous and decline in size of CMOS circuits and frequency at which circuits are operating. High-speed divider is an significant issue of high-speed computing. This paper presents quaternary division algorithm .This algorithm involves detect zero circuit designed with transmission gate. This proposed algorithm is faster than binary division algorithm as well as radix 4 SRT division algorithm in terms of speed & power. This type of fast divider can be used for the design of Arithmetic Logic unit.

Design of 8-Bit ALU Design using GDI Techniques with Less Power and Delay

Arithmetic Logic Unit (ALU) is a substantial fragment of microchip. Cutting-edge computerized processors, legitimate and math activity accomplishes making use of ALU. This paper depicts an 8-Bit ALU operating with a lowest power 11-Transistor Full Adder (11-T FA) and Gate dispersion input (GDI) centered MUX. All structures were simulated using Tanner EDA software version-15 with 32 nanometer BSIM4 innovation. Execution examinations were furnished as for voltage, power, postponement and power delay item. In this paper 8-bit ALU operated in subthreshold region, selected 0.7 VDD for maintain the both power as well as delay. In 8-bit ALU of GDI proposed model, less than 82% power consumption reduced as compare with CMOS 8-Bit ALU due to voltage level improvement.

An Automatic Placement and Routing Methodology for Asynchronous SFQ Circuit Design

This article proposes an automatically placed and routed methodology for asynchronous single flux quantum (SFQ) circuits using passive transmission line lines and utilizing a commercial electronic design automation (EDA) tool, Cadence Innovus. At the cell level, dual rail SFQ asynchronous cells were developed to be implemented in the place and route methodology. Scripts were written that could convert any single rail netlist synthesized from behavioral Verilog using an EDA tool (such as Design Vision) containing single rail cells into dual rail asynchronous cells. Then, automatic placement and routing using Innovus was achieved through specific cell layout design choices that allowed the finished circuit design layout to pass checks by layout vs schematic and design rule check. Finally, back annotation was performed by reincorporating transmission line lengths from place and route stage in analog simulation to verify correct functionality of the design. As an example, a 4-b arithmetic logic unit design is used to illustrate the various stages of the methodology.

An unconventional Arithmetic Logic Unit design and computing in Actin Quantum Cellular Automata

An efficient design of basic Arithmetic Logic Unit (ALU), based on Actin based Quantum Cellular Automata (QCA), is presented in this paper. Boolean logic function has been realized by the collisions occur in molecular QCA network. Actin is found as thin helical filamentous form, consists of two protein chain built by its own monomer globular actin. Active participation of actin in signaling events of cytoskeleton has introduced the thought of constructing Boolean logic system in nano scale by itself. To realize the logic, filamentous actin is simulated by one dimensional partitioned QCA concept. As the width of F-Actin is only 7 nm, designing the logic circuits in high density with this unconventional technology will be more efficient than the conventional semiconductor technology. This proposed work will be illuminative in the field of unconventional computing.

ERSFQ 8-Bit Parallel Arithmetic Logic Unit

We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab's 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.