Based on FS-GDI Approach with 65 nm Technology: Low Power ALU Design

Abstract

ABSTRACT This paper presents an area/power efficient design for the Arithmetic Logic Unit (ALU) utilising the FS-GDI approach. The presented ALU is designed in 45 nm, 65 nm and 130 nm node using Cadence Virtuoso simulator. Various ALUI/ALUII designs are presented with different data words. The result of ALUI proves its superiority compared with the traditional CMOS-based design in terms of power consumption, propagation delay and transistor count. The energy of the proposed 4-bit ALU reduced by 32% compared to CMOS based. Scalability of the proposed ALUI and ALUII designs are tested by extending length of the processed bits to 32-bits, through testing the performance of 8-bit, 16-bit, 32-bit ALUs based on the proposed ALUI and ALUII design. It is seen that the energy of the 4-bit ALU reduced by 21.2%, the power efficiency of the DSP and image processing circuits can be improved utilising the proposed designs of the ALUs. The experiment clears the superiority of the proposed ALU units and its suitability for long data words.