Design Of Approximate Multipliers Research Articles

Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor

This paper proposes novel approximate 4:2 compressors developed using input reordering circuits and input combination probabilities. The input reordering circuit is used to reduce the hardware complexity of the proposed designs. This paper proposes two designs of approximate 4:2 compressors. This compressor is used in designing an approximate multiplier. The proposed multiplier designs utilize less energy than the already published ones due to acceptable inaccurate output/precision, which are best suitable for image processing applications. The proposed multiplier designs MUL1, MUL2, MUL3 and MUL4 saves 22.75%, 21.95%, 11.57%, and 8.95% energy than the best of the existing design 1.

Design and Analysis of Low Power Approximate Multiplier Using Novel Compressor

Design and Analysis of Low Power Approximate Multiplier Using Novel Compressor

A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits

Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.

Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI

Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI

Design and Analysis of Energy Efficient Approximate Multipliers for Image Processing and Deep Neural Network

Design and Analysis of Energy Efficient Approximate Multipliers for Image Processing and Deep Neural Network

Power–Area-Optimized Approximate Multiplier Design for Image Fusion

Power–Area-Optimized Approximate Multiplier Design for Image Fusion

A high speed and power efficient multiplier based on counter-based stacking

<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>

Design of area-efficient modified decoder-based imprecise multiplier for error-resilient applications

The imprecise multipliers are the building blocks of error-tolerated applications such as image processing. This article introduces area-efficient n×n approximation multipliers using a proposed 3-bit decoder logic algorithm. The theme of the work is to minimize the partial product rows effectively using the proposed algorithm, thereby simplifying the accumulation stage process. As a result, the suggested N×N imprecise multipliers reduce the design complexity. The suggested and existing circuits in the literature are simulated using the Cadence RTL compiler with TSMC 180 nm technology. Implementation outcomes indicate that the suggested 8 × 8 and one of the proposed 16 × 16 approximate multipliers achieve 46.70%, 45.96%, and 46.58%, 28.11% area and power reductions compared to the accurate multipliers. Compared with the exact multiplier, the suggested 8 × 8 approximate model reduces the Area-Delay Product (ADP) and Area-Delay-Power Product (ADPP) by 49.95% and 72.95%, respectively, with reasonable error metrics. Also, the proposed 16 × 16 approximate multipliers maintain a better performance balance between area demand and allowable error rate. Moreover, while extending in image multiplication, smoothing and sharpening, the 8 × 8 proposed approximate multiplier attains an acceptable mean structural similarity index value with less area requirement than previous approximate multiplier designs.

Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Finite Impulse Response (FIR) filter contributes a major role in most of the signal processing applications. However, the Finite Impulse Response filter performance is restricted by its speed, power and area usage. To address these issues, an adaptive FIR filter design using approximate adder and Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier (DA-AFIR-leadx-hybam-AC) is proposed in this manuscript for eradicating the noise in the sensor nodes. Here, Low error together with area efficient approximate adder (leadx) is used for reducing path delay and area utilization. For approximate multiplier design, proposed Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier using 15–4 Approximate Compressors (hybam-AC) is used for decreasing power consumption and design complexity. The simulation of the proposed model is implemented in Verilog and the design is synthesized in FPGA utilizing Xilinx ISE 14.5. The proposed DA-AFIR-leadx-hybam-AC filter design attains 33.6%, 22.75%, 29.69% lower power and 43.58%, 11.3%, 33.07% lower delay than the existing approaches, like DA-AFIR-MLDA-RNS, DA-AFIR-Hyb-CSD-ABR, DA-AFIR-SOPOT-MPGBP. Finally, the proposed DA-AFIR-leadx-hybam-AC filter design is applied for noise removal application in sensor nodes. The proposed Filter is implemented in MATLAB/Simulink for reading input signal.

Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs

Domain-specific accelerators for signal processing, image processing, and machine learning are increasingly being implemented on SRAM-based field-programmable gate arrays (FPGAs). Owing to the inherent error tolerance of such applications, approximate arithmetic operations, in particular, the design of approximate multipliers, have become an important research problem. Truncation of lower bits is a widely used approximation approach; however, analyzing and limiting the effects of carry-propagation due to this approximation has not been explored in detail yet. In this article, an optimized carry-aware approximate radix-4 Booth multiplier design is presented that leverages the built-in slice look-up tables (LUTs) and carry-chain resources in a novel configuration. The proposed multiplier simplifies the computation of the upper and lower bits and provides significant benefits in terms of FPGA resource usage (LUTs saving 38.5%–42.9%), Power Delay Product (PDP saving 49.4%–53%), performance metric (LUTs × critical path delay (CPD) × PDP saving 68.9%–73.1%) and errors (70% improvement in mean relative error distance) compared to the latest state-of-the-art designs. Therefore, the proposed designs are an attractive choice to implement multiplication on FPGA-based accelerators.

Design of imprecise compressor applications based on Hazy-Multipliers

Approximate multipliers are a trending digital design that was specially developed for the implementation of low power and high-speed circuits. The main purpose of this design is to trade the necessity of accurate multipliers. In this work, a novel imprecise compressor was designed to develop the Hazy Multipliers for low-error resilient applications. These imprecise compressors are synthesized using a 40 nm CMOS technology. When compared with the previous approximate multiplier design the proposed Hazy Multipliers are can reduce the error up to 96%, 98.9%, 99.5% respectively than the existing methods. Finally, the proposed design is investigated on the image smoothening application to show the performance metrics of Hazy Multipliers.

Design and Analysis Of Approximate Multiplier With Reconfigurable Reduction

Design and Analysis Of Approximate Multiplier With Reconfigurable Reduction

Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors

Approximate computing is a promising approach for reducing power consumption and design complexity in applications that accuracy is not a crucial factor. Approximate multipliers are commonly used in error-tolerant applications. This paper presents three approximate 4:2 compressors and two approximate multiplier designs, aiming at reducing the area and power consumption, while maintaining acceptable accuracy. The paper seeks to develop approximate compressors that align positive and negative approximations for input patterns that have the same probability. Additionally, the proposed compressors are utilized to construct approximate multipliers for different columns of partial products based on the input probabilities of the two compressors in adjacent columns. The proposed approximate multipliers are synthesized using the 28nm technology. Compared to the exact multiplier, the first proposed multiplier improves power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> delay and area <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> power by 91% and 86%, respectively, while the second proposed multiplier improves the two parameters by 90% and 84%, respectively. The performance of the proposed approximate methods was assessed and compared with the existing methods for image multiplication, sharpening, smoothing and edge detection. Also, the performance of the proposed multipliers in the hardware implementation of the neural network was investigated, and the simulation results indicate that the proposed multipliers have appropriate accuracy in these applications.

Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

Partial products of higher radix are approximated by partial product segmentation. The encoder skips few lower order bits to segment the partial products for approximation. For a particular type of approximation, one can have many options of choosing the higher radix for hybrid encoding. However, the selection of higher radix is the key to obtain an optimal approximate hybrid multiplier design. In this paper, we made an in-depth study on radix-64 and radix-256 encoding for 4-bit and 5-bit approximations. Proposed a two-term radix-64 encoding and three-term radix-256 encoding for 4-bit approximation to calculate partial-products with lowest maximum absolute error (MAE). Further, we have proposed a simple rule to select the higher radix for hybrid encoding to obtain an efficient approximate multiplier design. To demonstrate the usefulness of the selection rule, two hybrid encoding schemes named R4R64 and R4R256 are formulated by combining radix-4 separately with proposed two-term radix-64 and three-term radix-256 encoding schemes. Separate multiplier designs are derived using the proposed hybrid encoding. Comparison result shows that both the proposed approximate multipliers have identical output accuracy, but the multiplier design based on proposed hybrid R4R64 encoding is more hardware efficient than the other. Compared with the existing approximate multiplier based on hybrid R4R256 encoding for word-length 12, the proposed multiplier design based on R4R64 hybrid encoding involves nearly 15% less area-delay product (ADP) and a marginal 4% less power-delay-product (PDP), but calculates output with higher accuracy. The 2-D DCT structure using proposed R4R64 multiplier involves 13% lesser ADP and 14% less energy consumption when compared with the 2-D DCT structure based on existing hybrid R4R256 multiplier design and computes reconstructed images with nearly 10dB higher pick signal-to-noise ratio (PSNR).

Exact and approximate multiplications for signal processing applications

Approximate computing is an emerging technique that can be used for developing power, area and delay efficient circuits at the cost of loss of accuracy. This paper investigates the possibility of efficient exact multipliers through the use of improved compressors and counters and thereafter deriving approximate multiplier structures to achieve a higher percentage of logic optimization at the expense of the lowest possible error. NAND gate based array structure with reduced complexity is used for generating the partial products for both the exact and approximate multipliers. Two variants of the efficient exact multiplier are proposed. The proposed exact multiplier EM-1 is area and power efficient, whereas EM-2 is delay and energy efficient. Two variants of 4:2 compressors are introduced for developing approximate multipliers. The proposed multipliers excel most of the state-of-the-art existing multipliers in terms of the important performance metrics. The proposed exact and approximate multiplier designs are employed for developing ECG denoising FIR filter for the elimination of power line interference and the corresponding performance improvement is illustrated. Cadence RTL compiler v11.10 with GPDK 45 nm standard cell library is used for the synthesis. The simulation of all the multipliers is done by running a test bench program using modelsim.

An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy. To overcome these issues, the digital circuits are applied to the Deep Learning (DL) approaches for higher accuracy. In recent times, DL is the method that is used for higher learning and prediction accuracy in several fields. Therefore, the Long Short-Term Memory (LSTM) is a popular time series DL method is used in this work for approximate computing. To provide an optimal solution, the LSTM is combined with a meta-heuristics Jellyfish search optimisation technique to design an input aware deep learning-based approximate multiplier (DLAM). In this work, the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier. The optimal hyperparameters of the LSTM model are identified by jelly search optimisation. This fine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy. The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a function of area, delay, power and error metrics. The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approximate computing multiplier achieved a superior area and power reduction with very good results on error rates.

DESIGN AND IMPLEMENTATION OF A NOVEL ENERGY-EFFICIENT MULTIPLIER CIRCUIT USING APPROXIMATE COMPUTING TECHNIQUE

A promising paradigm for many imprecision-tolerant applications has recently been identified as approximate arithmetic. By reducing accuracy standards, it can significantly reduce circuit complexity, latency, and energy consumption. In this research, we present a unique significance-driven logic compression (SDLC) approach for an energy-efficient approximate multiplier design. An algorithmic and adjustable lossy compression of the partial product rows based on their progressive bit importance is the core of this approach. To lessen the number of product rows, the resulting product terms are then commutatively remapped. As a result, the multiplier's complexity in terms of the number of logic cells and the lengths of critical routes is significantly decreased.

Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, an open-source adaptable approximate multiplier design driven by input distribution and polarity is proposed to generate optimized approximate multipliers to trade off between the application-level performance and the hardware cost. The proposed method minimizes the average square of the absolute error of an approximate multiplier according to the probability distributions of operands extracted from the target application with consideration of input polarity, achieving low hardware cost and negligible application-level performance loss. The proposed method can generate unsigned multipliers (or signed multipliers) based on the Braun multiplier (or Baugh–Wooley multiplier). To demonstrate the effectiveness of the method, three different-scale quantized DNNs, including LeNet, AlexNet, and VGG16 with 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 8 unsigned multiplication and an adaptive least mean square (LMS)-based finite impulse response (FIR) filter with 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 16 fixed-point signed multiplication, are evaluated. In the DNN training process, a noise training technique is adopted to reduce the accuracy loss due to the approximation. When compared to the state-of-the-art approximate multipliers, the generated multipliers can achieve up to 26.4% and 27.1% product of power, delay, and area gains with negligible application-level performance loss in VGG16 and FIR applications, respectively.

Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm

Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm