Design of area-efficient modified decoder-based imprecise multiplier for error-resilient applications

Abstract

The imprecise multipliers are the building blocks of error-tolerated applications such as image processing. This article introduces area-efficient n×n approximation multipliers using a proposed 3-bit decoder logic algorithm. The theme of the work is to minimize the partial product rows effectively using the proposed algorithm, thereby simplifying the accumulation stage process. As a result, the suggested N×N imprecise multipliers reduce the design complexity. The suggested and existing circuits in the literature are simulated using the Cadence RTL compiler with TSMC 180 nm technology. Implementation outcomes indicate that the suggested 8 × 8 and one of the proposed 16 × 16 approximate multipliers achieve 46.70%, 45.96%, and 46.58%, 28.11% area and power reductions compared to the accurate multipliers. Compared with the exact multiplier, the suggested 8 × 8 approximate model reduces the Area-Delay Product (ADP) and Area-Delay-Power Product (ADPP) by 49.95% and 72.95%, respectively, with reasonable error metrics. Also, the proposed 16 × 16 approximate multipliers maintain a better performance balance between area demand and allowable error rate. Moreover, while extending in image multiplication, smoothing and sharpening, the 8 × 8 proposed approximate multiplier attains an acceptable mean structural similarity index value with less area requirement than previous approximate multiplier designs.