Efficient and low-cost approximate multipliers for image processing applications

Abstract

The image processing can be implemented in an error-tolerant mode with acceptable accuracy. In digital image processing, the adders and multipliers are the most important components. In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and 4:2 compressor, respectively. In the structure of the proposed multipliers, we have adders for the addition of two multiple-bit numbers. In the adder structure, the full adders are designed based on two modified half adders and one NAND gate. The proposed approximate 4:2 compressor and two approximate 4-bit full adders are compared from hardware and accuracy point of view such as gate count, area-delay product (ADP), error rate (ER), mean error distance (MED), mean relative error distance (MRED), and normalized error distance (NED). The efficacy of proposed multipliers in image processing applications such as image multiplication is evaluated using MATLAB. The results show the proposed approximate multipliers are comparable in terms of area, delay, and mean structural similarity index metric (MSSIM) parameter with other works.