Design Of Adder Circuit Research Articles

Exploring FinFET and GNRFET with a Study of Full Adder Circuit Design

Exploring FinFET and GNRFET with a Study of Full Adder Circuit Design

A comprehensive analysis of ultra low power GNRFET based 20T hybrid full adder for computing applications

In an era where energy efficiency is as important as computational speed, this paper introduces a new full adder circuit design that effectively integrates dynamic power gathering (DPG) power conservation benefits with XOR-XNOR pass-transistor logic (PTL) area and performance efficiencies using graphene nanoribbon field-effect transistors. GNRFETs are useful for digital logic due to their high carrier mobility and tunable bandgap. The paper describes the circuit’s seamless transition full adder response, demonstrating the tri-mode dynamic power gating strategy capacity to reduce static power depletion. The proposed hybrid full adder performs well with 7.76 nW power consumption, 481 ps latency, and 3.73 aJ PDP. This reduces power consumption by 99.9%, delay by 99.0%, and PDP by 99.8% compared to other adders. The effects of temperature, voltage, Noise immunity and Carry Forward Adders integration on power, delay, and PDP are also analysed, proving the design’s robustness. The adaptability of our full adder architecture allows its implementation in more complicated arithmetic and logic units, indicating a scalable and energy-efficient paradigm for future integrated circuits.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

The goal of this research is to create Full-Adder gate using a Complementary Metal Oxide Semiconductor (CMOS) and an Artificial Neural Network.We constantly bear in mind that any COMS circuit we design should be as inexpensive as possible.Multilayer ANN was employed in this work to create the circuit. Weights are employed to modify the value in our study, treating neurons as transistors and treating negative values as inverters.We are also designing Verilog-HdL Code to simply apply the full adder for experimenting an artificial neural network assigning weights to get appropriate results. Keywords: Full Adder, CMOS,ANN,Verilog-HDL

The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology

The complexity of digital circuits is constantly rising. Analog computing can be an excellent alternative to overcome the complexity issue. Operational Amplifiers play a serious role in many analog circuit designs. This paper presents a new implementation approach to an analog subtractor. This design enjoys high speed and low power dissipation using Carbon Nanotube FETs (CNTFETs). We have also achieved a significant improvement in terms of the number of transistors and chip area. The proposed design considerably decreases power consumption and optimizes the chip area. The same performance can be achieved when designing a high-quality Differentiator. It is to remark that there is no need to use a huge number of resistors and capacitors. In this design, no additional voltage or current sources have been used. HSPICE and the Stanford 32 nm CNTFET model are used to simulate the proposed circuit. The comparisons with State-of-the-art prove the performance of this design.

Design and implementation of a Low power Adder Circuit Using LECTOR Technique

This work implements a 1-bit FA circuit with the CMOS logic with XOR-XNOR combinations. For sum and carry, pass transistors are used to generate the output by combining with XOR, XNOR and CMOS design, and the optimised full adder is implemented with the help of LECTOR technique to control the leakage power. As scaling of CMOS technology has shown improvement in the speed but the leakage power are left to act as major effect. low power VLSI is a new discipline in which high power consumption is becoming an important criteria. But when refers to battery life, high power dissipation is not recommended for device applications. It affects performance, raises cooling expenses, and shortens battery capacity. The switching, dynamic and leakage power changes the inputs significantly. There are several typical reduction strategies available to lower the energy of circuits. By implementing the reduced FA with the leakage power control technique the number of transistors reduced than the normal full adder. The proposed design has static and total power of 5.08nw and 8.33uw for XNOR and for XOR of 12.36nw and 8.56uw. A FA is designed using these technique the obtained results for static and total power are 12.38uw 8.58uw. For the above circuits, a comparison of various static and total power dissipations is conducted. CADENCE-VIRTUOSO is used to simulate circuits using 90nm technology with a 1.2V power supply.

LOW POWER OPTIMIZATION OF FULL ADDER CIRCUIT BASED ON GDI LOGIC FOR BIOMEDICAL APPLICATIONS

Advanced Electronic Devices have recently become more prevalent, designers have opted for low power, quick speed, and compact designs and processes. Even though there are numerous design methodologies currently in use for VLSI system design optimization, very few design techniques produce solutions that are optimally optimal. GDI-based circuits are becoming increasingly important since they use less space, power, and energy. The GDI technique ensures minimal propagation delay, power, and area in low-power design strategies. For 45nm technology, the Cadence Virtuoso EDA tool is utilised to determine delay and power. The proposed designs examination of delay and power performance at 1.0V voltage produced positive findings. The Gate Diffusion Input concept serves as the foundation for the proposed design in this work. In order to achieve a full voltage swing of the output, a 1-bit full adder circuit design using GDI is demonstrated in this work. The GDI with the Full Swing Technique is presented in this work. Applying the suggested way to a 45nm complete adder from 14 Transistors. It is evident from the obtained simulation results that the suggested design uses the least power and the least amount of delay when compared to other full adder circuits that are already in use. Consequently, compared to previous full adder GDI circuit designs, the output voltage swing is in full and the overall power-delay product is improved by 60 percent.

A novel pipelined carry adder design based on half adder

<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone IV FPGA kit platform. Results show that the circuit needs a 7.69 ƞ Sec delay time to provide the output values. The suggested PCA circuit is more attractive than the conventional ripple carry adder for future electronic applications. </span>

An efficient QCA-based full adder design with power dissipation analysis

ABSTRACT Quantum Dot-Cellular automata (QCA) is a developing technology that is considered as the best viable alternate solution for CMOS technology which has short-channel effects. QCA is a transistor-free technology, and the information is distributed formulated on the charge of the electron and by Columbic repulsion theory. In this paper, an optimal adder circuit is proposed using QCA technology which consist only 14 cells. The proposed adder circuit is further utilised for designing of 4-bit adder design efficiently. Simulations results, are obtained precisely using QCADesigner software version 2.0.3., confirm that the proposed circuits work well. Moreover, the energy dissipations of the proposed adder circuit design is estimated using QCAPro tool. The performance of the proposed design was compared with the existing ones which shows better performance in terms of cell count, area, and latency. Suggested 1-bit and 4-bit QCA adders exhibit a delay of 0.5 and 1.25 clock cycle, occupy an active area of 0.01 and 0.1 and μm2, and use 14 and 84 QCA cells, respectively.

An energy efficient high-speed quantum-dot based full adder design and parity gate for nano application

Quantum-dot cellular automata (QCA) are novel prominent emerging nano-computational nanoelectronics technology at the nanoscale. It facilitated computation paradigms and promises an alternative good solution to traditional transistor CMOS technology with faster speed, very low energy dissipation, higher scale integration, small size, low latency/delay of circuits, and higher switching frequency. It is one of the most valuable nanotechnologies (or Nanotech) that effort to fabricate general computational at the nanoscopic-scale by commanding the position of electrons. In this paper, we have proposed the design of novel robust full adder, testable even and odd parity circuits using coplanar single layer in quantum-dots cellular automata nanotechnology. The proposed design of full adder circuits used only 36 quantum dots cells, occupied a design area of 0.04 µm2, and minimum delay count is 0.75 clock cycles. The proposed circuit’s investigated by novel QCADesigner-E (Energy) tool on using coherence vector (w/Energy) engine and optimized the energy-dissipation (ED) of full adder circuit. In the proposed design do not use coplanar multilayer and 45-degree rotated cells but used regular synchronized clock cycle and minimum quantum-dots cells. Therefore overall manufacturability of the robust full adder circuits significantly more improves as compared to the existing design. The presented robust full adder design have been calculated the total ED (Sum_Ebath) is 1.70e−002 eV (Error: +/- −1.63e−003 eV), and average ED/cycle (Avg_Ebath) is 1.54e−003 eV (Error: +/- −1.48e−004 eV).

HALF ADDER DESIGN USING VARIOUS TECHNOLOGIES AND COMPARISON OF

: In this paper, investigate and analysis various techniques for implementing a half adder circuit with the fewest transistors possible. In digital electronics half adder combinational circuit used to add two numbers. It is an arithmetic circuit that performs the arithmetic operation of adding two single-bit words. The half adder technique, design of half adder using AVL technology, Design of a 3-T Half Adder, NMOS pass transistors logic design of half adder using 2:1 MUX, half adder circuit design with CMOS NAND gates, half adder circuit design with CMOS transmission logic gates in cadence virtuoso. In this section, compare half adder circuit design techniques and compare various parameters of half adder circuit design used various circuit design techniques. Conventional techniques required fewer number routing resources. A 3-T halfadder circuit performs with less delay, high speed, small layout area, less power consumption and batter efficiency and accuracy

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs. Moreover, these advantages are achieved over a wide supply voltage range, operating temperatures, and output loads. The design is also more robust to process variations than the nearest design in terms of PDP.

Design and Implementation of Quantum half Adder and Full adder Using IBM Quantum Experience

Quantum machine learning is the combination of quantum computing and classical machine learning. It helps in solving the problems of one field to another field. Quantum computational power can be advantageous in handling huge data at a faster rate.In this regard, quantum computational power can be advantageous in handling such huge data at a faster rate. Classical machine learning is about trying to find patterns in data and using those patterns to predict future events. Quantum systems, on the other hand, produces typical patterns which are not producible by classical systems, thereby postulating that quantum computers may overtake classical computers on machine learning tasks. Hence the whole motivation in this work is on understanding and analysing the half adder and full adder circuit design using Quantum mechanics.

Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

PurposeIn nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits.Design/methodology/approachThis paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration.FindingsA new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level.Originality/valueThis paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

Design and analysis of QCA adder circuits for efficient computation

QCA technology is considered a viable alternative for CMOS technology since it solves most of the CMOS implications. The Quantum dot Cellular Automata is a computer software program that relates a discrete dynamical system with quantum mechanics. Quantum mechanics is a kind of physics about subatomic particles and which has many interesting properties. The QCA offers very great switching speed and consumes power dissipation extensively. The logic circuits play an essential role in the branch of computer arithmetic. In this paper, the adder circuits have been designed using the novel transistor-free technology called QCA. In addition to that, the planned work has been investigated with CMOS technology. The proposed work is simulated and synthesized by QCA designer suit 2.0.3.

Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit

This paper presents a novel energy efficient logic called Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) operating using four phase power clock sources. The CSIPGL based circuit is capable of operating through a wider range of frequency from 100MHz to 1GHz. CSIPGL logic has been designed using UMC 90nm technology model files and are simulated using Cadence® Virtuoso EDA tools. Efficiency of CSIPGL circuit is validated by comparing it against CSSAL, SQAL, SyAL, adiabatic logic circuits based on single charge sharing transistor [14] and EE-SPFAL circuit designs. Power consumption of AND/NAND and XOR/XNOR sub modules used in the design of 4-bit Carry Lookahead Adder circuits (CLA) are compared. 4-bit CLA is taken as a benchmark circuit to validate the efficiency of the proposed CSCPAL circuit.

Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique

For computational arithmetic, a full adder is the primary logic units in VLSI applications. A new full adder circuit design has been presented in this article which is based on input switching activity pattern and gate diffusion input (GDI) technique. The adder has been designed in two stages. The first stage is an XOR–XNOR module, whereas, the final stage is for the required outputs. By using the switching activity pattern of inputs and GDI techniques at each stage, the switching activities of the transistors have been minimized. This improves delay, power consumption and computational complexity. The adder has been designed and evaluated by using the synopsis tool and compared with different existing adder cells found in the literature. It is found that the presented adder shows an improvement at least 72.86% and 66.67% in terms of speed and energy consumption, respectively. Extensive performance analyses of the full adder have also been evaluated at 32 nm CMOS and 32 nm CNFET technology node which shows promising performances in both the technology nodes.

Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology

Quantum-dot Cellular Automata (QCA) is a new technology for designing digital circuits in Nanoscale. This technology utilizes quantum dots rather than diodes and transistors. QCA supplies a new computation platform, where binary data can be represented by polarized cells, which can define by the electron’s configurations inside the cell. This paper explains QCA based combinational circuit design; such as half-adder and full-adder, by only one uniform layer of cells. The proposed design is accomplished using a novel XOR gate. The proposed XOR gate has a 50% speed improvement and 35% reduction in the number of cells needed over the best reported XOR. The results of QCADesigner software show that the proposed designs have less complexity and less power consumption than previous designs.

Fast Mux-based Adder with Low Delay and Low PDP

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into several sub-blocks and the circuit of each sub-block is designed based on multiplexers and NOR gates to calculate the output carry or input carry of the next sub-block. This method reduces critical path delay (CPD) and therefore increases the speed of the adder. Simulation and synthesis of the proposed adder is done for cases of 8, 16, 32, and 64 bits and the results are compared with those of other fast adders. Synthesis results show that the proposed 16 and 32-bit adders have the lowest computation delay and also the best power delay product (PDP) among all recent popular adders.

Quadruple half adder and half subtractor design using SLM and Savart plate

This paper proposes quadruple half adder and half subtractor circuit design using spatial light modulator (SLM) and Savart plate. Over the last 2 decades, advanced technology at high-speed computation has generated large volumes of data. For some novel approaches in data processing techniques to deal with this large number of data, the ultra-high speed data processing system is required. Now optical multiple-valued logic functions are of greatest interest in recent years towards optical logic and information processing system. In order to overcome the electronic bottlenecks and fully exploit the advantages of optics, polarization properties of light realization come from nonlinear optics. It increases the scope of all-optical signals processing in high-speed photonic networks. To this aim, the designs need the use of nonlinear optics capable of controlling multi-valued signals. And to achieve this goal, the polarization properties of light in optical domain are used to the design of quadruple half adder half subtractor circuits.