Finite State Machine Description Research Articles

Synchronization of Variable-Length Constrained Sequence Codes

We study the ability of recently developed variable-length constrained sequence codes to determine codeword boundaries in the received sequence upon initial receipt of the sequence and if errors in the received sequence cause synchronization to be lost. We first investigate construction of these codes based on the finite state machine description of a given constraint, and develop new construction criteria to achieve high synchronization probabilities. Given these criteria, we propose a guided partial extension algorithm to construct variable-length constrained sequence codes with high synchronization probabilities. With this algorithm we construct new codes and determine the number of codewords and coded bits that are needed to recover synchronization once synchronization is lost. We consider a large variety of constraints including the runlength limited (RLL) constraint, the DC-free constraint, the Pearson constraint and constraints for inter-cell interference mitigation in flash memories. Simulation results show that the codes we construct exhibit excellent synchronization properties, often resynchronizing within a few bits.

Technology Mapping of FSM Oriented to LUT-Based FPGA

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

Correlated biased random walk with latency in one and two dimensions: Asserting patterned and unpredictable movement

The correlated biased random walk with latency in one and two dimensions is discussed with regard to the portion of irreducible random movement and structured movement. It is shown how a quantitative analysis can be carried out by using computational mechanics. The stochastic matrix for both dynamics are reported. Latency introduces new states in the finite state machine description of the system in both dimensions, allowing for a full nearest neighbor coordination in the two dimensional case. Complexity analysis is used to characterize the movement, independently of the set of control parameters, making it suitable for the discussion of other random walk models. The complexity map of the system dynamics is reported for the two dimensional case.

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits

A formal verification method of the datapath and controller generation phase of a high-level synthesis (HLS) process is described in this paper. The goal is achieved in two steps. In the first step, the datapath interconnection and the controller finite state machine description generated by a high-level synthesis process are analyzed to obtain the register transfer-operations executed in the datapath for a given control assertion pattern in each control step. In the second step, an equivalence checking method is deployed to establish equivalence between the input and the output behaviors of this phase. A rewriting method has been developed for the first step. Unlike many other reported techniques, our method is capable of validating pipelined and multicycle operations, if any, spanning over several states. The correctness and complexity of the presented method have been treated formally. The method is implemented and integrated with an existing HLS tool, called structured architecture synthesis tool. The experimental results on several HLS benchmarks indicate the effectiveness of the presented method.

The Crystallizing Substochastic Sequential Machine Extractor: CrySSMEx

This letter presents an algorithm, CrySSMEx, for extracting minimal finite state machine descriptions of dynamic systems such as recurrent neural networks. Unlike previous algorithms, CrySSMEx is parameter free and deterministic, and it efficiently generates a series of increasingly refined models. A novel finite stochastic model of dynamic systems and a novel vector quantization function have been developed to take into account the state-space dynamics of the system. The experiments show that (1) extraction from systems that can be described as regular grammars is trivial, (2) extraction from high-dimensional systems is feasible, and (3) extraction of approximative models from chaotic systems is possible. The results are promising, and an analysis of shortcomings suggests some possible further improvements. Some largely overlooked connections, of the field of rule extraction from recurrent neural networks, to other fields are also identified.

MULTILEVEL SYNTHESIS OF FINITE STATE MACHINES BASED ON SYMBOLIC FUNCTIONAL DECOMPOSITION

This paper presents a Finite State Machine (FSM) implementation method based on symbolic functional decomposition. This novel approach to multilevel logic synthesis of FSMs targets Field Programmable Gate Array (FPGA) architectures. Traditional methods consist of two steps: internal state encoding and then mapping the encoded state transition table into target architecture. In the case of FPGAs, functional decomposition is recognized as the most efficient method of implementing digital circuits. However, none of the known state encoding algorithms can be considered as a good method to be used with functional decomposition. In this paper, the concept of symbolic functional decomposition is applied to obtain a multilevel structure that is suitable for implementation in FPGA architectures. The symbolic functional decomposition does not require a separate encoding step. It accepts FSM description with symbolic states and performs decomposition, producing such a state encoding that guarantees the optimal or near-optimal solution.

Closed queueing network models of interacting long-lived TCP flows

This paper presents a new analytical model for the estimation of the performance of TCP connections. The model is based on the description of the behavior of TCP in terms of a closed queueing network. The model is very accurate, deriving directly from the finite state machine description of the protocol. The assessment of the accuracy of the analytical model is based on comparisons against detailed simulation experiments developed with the ns-2 package. The protocol model interacts with an IP network model that can take into account meshed topologies with several bottlenecks. Numerical results indicate that the proposed closed queueing network model provides accurate performance estimates in all situations. A novel and interesting property of the model is the possibility of deriving ensemble distributions of relevant parameters, such as, for instance, the transmission window size or the timeout probability, which provide useful insight into the protocol behavior and properties.

Self‐checking Synchronous FSM Network Design with Low Overhead

A method of a self‐checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self‐checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so‐called unate Programmable Logic Array (PLAu) description. Single stuck‐at fault on the FSM poles and gate poles are considered. PLAu realization of FSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLAu realization is derived from the State Transition Graph (STG) description of FSMs with using the m‐out‐of‐n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self‐checking one with low overhead is discussed.

SOLiT: An automated system for synthesising reliable sequential circuits with multilevel logic implementation

The paper presents SOLiT, an automated system for synthesising reliable sequential circuits with multilevel logic implementation. The reliability enhancement is achieved by using concurrent error detection scheme with coding techniques. The system receives the behavioural description of finite-state machines, determines the required checker circuits, and generates the physical layouts. The synthesised circuits can detect multiple unidirectional errors. A novel output partitioning algorithm is presented to reduce the hardware cost of the required checker circuits. Results show that the overhead for reliability enhancement of the synthesised sequential circuits is relatively low.

A Finite State Machine Compiler and Simulator

Finite State Machine (FSM) is an important element in digital systems design and in the design of VLSI systems. In any digital system which is not purely combinational, FSM design is essential. The FSM comprises of combinational logic with both independent and output dependent inputs. Some outputs from the combinational logic are fed back to the input side in order to generate the required number of finite states (there may be outputs which are not fed back). This article describes the FSM compiler implemented at CEERI's VLSI Design Centre and the associated simulator. The input to the FSM compiler is in an easy-to-use FSM description language. The simulator for the FSM is transition-table driven. The novel feature of the simulator is that it allows the user to define an output command dictionary which aids the system designer's job of debugging and testing the command outputs of the FSM.

Optimizing interacting finite state machines using sequential don't cares

Approaches are presented to multilevel sequential logic synthesis-algorithms and techniques for the area and performance optimizations of interconnected finite state machine descriptions. Techniques are presented for the exploitation of sequential don't cares in arbitrary, interconnected sequential machine structures. Exploiting these don't care sequences can results in significant improvements in area and performance. The problem of moving logic across state machine boundaries so as to make particular machines less complex at the possible expense of making others more complex is addressed. Optimization algorithms that incrementally modify state machine structures across latch boundaries are also presented. The use of more global state machine decomposition and factorization algorithms for area optimization is described, and experimental results using these algorithms on sequential circuits are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Speed tunable finite state machine compiler: Zephcad

The paper describes a personal computer based state machine compiler. This system transforms the finite state machine description, Boolean equations or truth table into net lists of a CMOS gate array or standard cell. A feature of this system is the capability to tune the circuit speed from the user side by selecting the number of logic levels when running the system. Benchmark results are included.

Some results on the design of regular structured sequential circuits

A modern trend in the design philosophy of digital systems is to build up a system using only few different types of subsystems, and to minimize the information flow between the instances of these Subsystems. Hitherto the definition of the behaviour of a subsystem and the construction of the system structure is carried out intuitively. For the case of a finite state machine description and exemplified with a counter design, we present some results towards a formal logic design methodology. The theory is based on the algebraic structure theory of Hartmanis and is aimed at wiring identical subsystems by abutment.