FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Nitish Das,P Aruna Priya

doi:10.1155/2018/6831901

Nitish Das, P Aruna Priya

Open Access

https://doi.org/10.1155/2018/6831901

Copy DOI

Abstract

The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

Highlights

Designing a complex digital system requires an efficient method that includes modeling a control unit
The Reconfigurable FSM with input multiplexing (FSMIM)-S architecture is constructed by combining the conventional FSMIM with state-based input selection (FSMIM-S) architecture [10] and an optimized multiplexer bank
The experimental results from MCNC finite state machine (FSM) benchmarks illustrate the advantages of the proposed architecture as compared with variation-based reconfigurable multiplexer bank (VRMUX) [11], as operating speed is enhanced at an average of 30.43% and LUT consumption is reduced by an average of 5.16% in field programmable gate array (FPGA) implementation

Summary

Introduction

Designing a complex digital system requires an efficient method that includes modeling a control unit (i.e., a controller). The mathematical model for designing a controller for applications such as microprocessor control units, circuit testing, and digital signal processing (DSP) is a finite state machine (FSM) Designing such systems requires an efficient synthesis technique for high-speed FSM [1, 2]. FSMIM with state-based input selection (FSMIM-S) is proposed in [10], which further reduces the ROM memory size Another approach for implementation of reconfigurable FSM is RAM-based architectures. The experimental results from MCNC FSM benchmarks illustrate the advantages of the proposed architecture as compared with VRMUX [11], as operating speed is enhanced at an average of 30.43% and LUT consumption is reduced by an average of 5.16% in FPGA implementation.

Proposed Method

Experimental Evaluation

Findings

Concluding Remarks