Circuit Description Research Articles

Algorithms for extracting subsystems from a multilevel representation of a system of Boolean functions for joint minimization

Objectives. The purpose of experimental research is to determine the effectiveness of new algorithms for extracting the so-called connected subsystems from formula descriptions of the original system of Boolean functions. Subsequently each of the extracted subsystems is minimized independently of the others, but the functions that make up each connected subsystem are minimized jointly.Methods. Minimization of subsystems is performed in the class of multilevel BDD representations (BDD – Binary Decision Diagram) or Boolean networks. After obtaining minimized descriptions of circuits, specified as a set of interconnected Shannon expansion formulas that correspond to BDD, or as two-operand logical equations corresponding to Boolean networks, synthesis of logic circuits is carried out in the design library of custom digital CMOS ASIC (Application-Specific Integrated Circuits made using complementary metal oxide semiconductor technology). In Boolean networks, node functions can be the logical operations “conjunction” or “disjunction” over literals of Boolean variables. A literal is a Boolean variable or its inversion. Minimization of BDD representations is carried out according to the number of Shannon decomposition formulas, minimization of Boolean networks – according to the number of literals in the formulas defining the networks.Results. The resulting logic circuits are compared in terms of chip area and speed (time delay). Experiments were carried out on 39 industrial circuit examples. The advantage (in 29 cases) of using the proposed subsystem extraction algorithms is shown compared to joint or separate minimization of the original system of Boolean functions, which is usually performed as the first stage of the synthesis of logic circuits.Conclusion. The new algorithms for subsystem extraction proposed in the paper have proven their effectiveness in the execution of various programs for optimizing multilevel representations of systems of Boolean functions. The developed software package allows improving the results of technologically independent optimization used in the implementation of digital system projects in custom digital CMOS ASIC.

Plant response to intermittent heat stress involves modulation of mRNA translation efficiency.

Acquired thermotolerance (also known as priming) is the ability of cells or organisms to survive acute heat stress if preceded by a milder one. In plants, acquired thermotolerance has been studied mainly at the transcriptional level, including recent descriptions of sophisticated regulatory circuits that are essential for this learning capacity. Here, we tested the involvement of polysome-related processes (translation and cotranslational mRNA decay (CTRD)) in Arabidopsis (Arabidopsis thaliana) thermotolerance using two heat stress regimes with and without a priming event. We found that priming is essential to restore the general translational potential of plants shortly after acute heat stress. We observed that mRNAs not involved in heat stress suffered from reduced translation efficiency at high temperatures, whereas heat stress-related mRNAs were translated more efficiently under the same condition. We also showed that the induction of the unfolded protein response (UPR) pathway in acute heat stress is favored by a previous priming event and that, in the absence of priming, ER-translated mRNAs become preferential targets of CTRD. Finally, we present evidence that CTRD can specifically regulate more than a thousand genes during heat stress and should be considered as an independent gene regulatory mechanism.

Algebraic Language for the Efficient Representation and Optimization of Quantum Circuits

Abstract The use of graphical language in quantum computing for the representation of algorithms, although intuitive, is not very useful for different tasks such as the description of quantum circuits in text environments, the calculation of quantum states or the optimization of quantum circuits. While classical circuits can be represented either by circuit graphs or by Boolean expressions, quantum circuits have until now predominantly been illustrated as circuit graphs because no formal language for quantum circuits that allows algebraic manipulations has so far been accepted. This work proposes a means to represent quantum circuits in a convenient and concise manner, similar to the way Boolean expressions are used in classical circuits. The proposed notation allows the consistent and parameterized description of quantum algorithms, as well as the easy handling of the elements that compose it to achieve powerful optimizations in the number of gates of the circuits. To visualize it, a software implementation of an algebraic quantum circuit framework has been made, which allows describing quantum circuits, as well as their respective state vectors, using the proposed algebraic language.

Power Quality Control Using Superconducting Magnetic Energy Storage in Power Systems with High Penetration of Renewables: A Review of Systems and Applications

The increasing deployment of decentralized power generation based on intermittent renewable resources to reach environmental targets creates new challenges for power systems stability. Several technologies and approaches have been proposed in recent years including the use of superconducting magnetic energy storage. This study focuses on the review of existing superconducting magnetic energy storage systems for power quality control purposes. Such systems can supply and absorb the rated power level within seconds, promoting fast power quality regulation. Systems for power quality services such as frequency regulation, power oscillation damping, power fluctuation suppression, and active power filtering are identified and described. First, the physical characterization of superconducting magnets concerning geometries, materials, associated inductances, and nominal magnetic energy storage capacities is conducted. Then, the functional description of several current conversion circuits and systems used as interfaces for superconducting magnets is performed. The existing methodologies and systems to perform the control of current converters for different power control services and applications are also identified and described. Finally, the results regarding the number of different systems identified for each power quality control service are presented, and their applicability is discussed based on the adopted control approach. Challenges concerning the development of new systems to improve the power quality on grids with high penetration of decentralized energy resources from intermittent renewables are also identified.

A Novel Common‐Ground Switched‐Capacitor Type Dual‐Mode Five‐Level Transformer‐Less Multilevel Inverter

ABSTRACTThis paper presents a novel single‐source common‐ground switched‐capacitor (CGSC) type dual‐mode five‐level (5L) transformer‐less (TL) multilevel inverter (MLI) topology with inherent boosting capability. The proposed topology comprises a single DC source, nine power switches, and two capacitors with self‐voltage balancing ability, reducing the inverter's size, cost, and complexity. The direct connection of the negative terminal of the source to the neutral point of the load eliminates the leakage current. The converter can operate in both buck and boost mode based on the series–parallel switching conversion of the involved switches. The circuit description, control strategy, and design guidelines are discussed in detail. The steady‐state and dynamic performance of the proposed circuit is validated using MATLAB Simulink software. Reliability analysis of the proposed converter is done in detail. Furthermore, the proposed converter is being compared with state‐of‐the‐art topologies.

Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions

Objectives. The problem of restoring the functional description of digital VLSI devices presented at the transistor level is considered. The objective of the work is to develop means for extraction of blocks representing logical networks from two-level descriptions of CMOS circuits at the transistor level, which were obtained as a result of recognition (extraction) of subcircuits that implement logic elements.Methods. Graph based methods and software tools are proposed for extracting a connected blocks representing a logical network from two-level descriptions of a transistor circuits in SPICE format. In the graph interpretation, the task is reduced to constructing a labeled directed graph of a logical network based on a labeled undirected bipartite graph specifying a two-level description of the transistor circuit.Results. The proposed method makes it possible to identify lexicographically ranked logical networks, from which a transition is made to logical equations that specify the functions implemented at the outputs of the resulting networks. Software tools have been developed that provide the generation of a hierarchical description in SPICE format that implements the original circuit at the transistor level, as well as descriptions of found logical networks in the SF language of hierarchical structural and functional descriptions of discrete devices and in high-level languages (VHDL and Verilog).Conclusion. The developed methods are implemented in C++, included in the program for decompiling transistor CMOS circuits and tested within it on practical examples of transistor-level circuits. The paper provides examples of reverse engineering of some practical transistor circuits.

Geometrical description and Faddeev-Jackiw quantization of electrical networks

In lumped-element electrical circuit theory, the problem of solving Maxwell's equations in the presence of media is reduced to two sets of equations, the constitutive equations encapsulating local geometry and dynamics of a confined energy density, and the Kirchhoff equations enforcing conservation of charge and energy in a larger, topological, scale. We develop a new geometric and systematic description of the dynamics of general lumped-element electrical circuits as first order differential equations, derivable from a Lagrangian and a Rayleigh dissipation function. Through the Faddeev-Jackiw method we identify and classify the singularities that arise in the search for Hamiltonian descriptions of general networks. The core of our solution relies on the correct identification of the reduced manifold in which the circuit state is expressible, e.g., a mix of flux and charge degrees of freedom, including the presence of compact ones. We apply our fully programmable method to obtain (canonically quantizable) Hamiltonian descriptions of nonlinear and nonreciprocal circuits which would be cumbersome/singular if pure node-flux or loop-charge variables were used as a starting configuration space. We also propose a specific assignment of topology for the branch variables of energetic elements, that when used as input to the procedure gives results consistent with classical descriptions as well as with spectra of more involved quantum circuits. This work unifies diverse existent geometrical pictures of electrical network theory, and will prove useful, for instance, to automatize the computation of exact Hamiltonian descriptions of superconducting quantum chips.

Monolith: Circuit-Friendly Hash Functions with New Nonlinear Layers for Fast and Constant-Time Implementations

Hash functions are a crucial component in incrementally verifiable computation (IVC) protocols and applications. Among those, recursive SNARKs and folding schemes require hash functions to be both fast in native CPU computations and compact in algebraic descriptions (constraints). However, neither SHA-2/3 nor newer algebraic constructions, such as Poseidon, achieve both requirements. In this work we overcome this problem in several steps. First, for certain prime field domains we propose a new design strategy called Kintsugi, which explains how to construct nonlinear layers of high algebraic degree which allow fast native implementations and at the same time also an efficient circuit description for zeroknowledge applications. Then we suggest another layer, based on the Feistel Type-3 scheme, and prove wide trail bounds for its combination with an MDS matrix. We propose a new permutation design named Monolith to be used as a sponge or compression function. It is the first arithmetization-oriented function with a native performance comparable to SHA3-256. At the same time, it outperforms Poseidon in a circuit using the Merkle tree prover in the Plonky2 framework. Contrary to previously proposed designs, Monolith also allows for efficient constant-time native implementations which mitigates the risk of side-channel attacks.

A new era of synthetic biology-microbial community design.

Synthetic biology conceptualizes biological complexity as a network of biological parts, devices, and systems with predetermined functionalities and has had a revolutionary impact on fundamental and applied research. With the unprecedented ability to synthesize and transfer any DNA and RNA across organisms, the scope of synthetic biology is expanding and being recreated in previously unimaginable ways. The field has matured to a level where highly complex networks, such as artificial communities of synthetic organisms, can be constructed. In parallel, computational biology became an integral part of biological studies, with computational models aiding the unravelling of the escalating complexity and emerging properties of biological phenomena. However, there is still a vast untapped potential for the complete integration of modelling into the synthetic design process, presenting exciting opportunities for scientific advancements. Here, we first highlight the most recent advances in computer-aided design of microbial communities. Next, we propose that such a design can benefit from an organism-free modular modelling approach that places its emphasis on modules of organismal function towards the design of multispecies communities. We argue for a shift in perspective from single organism-centred approaches to emphasizing the functional contributions of organisms within the community. By assembling synthetic biological systems using modular computational models with mathematical descriptions of parts and circuits, we can tailor organisms to fulfil specific functional roles within the community. This approach aligns with synthetic biology strategies and presents exciting possibilities for the design of artificial communities. Graphical Abstract.

“Mollusk-19” and “Mollusk-21” Autonomous Vertical Acoustic-Hydrophysical Measuring Systems

Autonomous vertical acoustic-hydrophysical measuring systems "Mollusk-19" and "Mollusk-21" are designed to study spatio-temporal inhomogeneities of the sound speed field and mode structures of low-frequency sound fields and internal waves. The article provides a description of circuit, design and software solutions that provided a solution to the main task posed during the development of new systems — improving their performance qualities. The possibilities of using systems to solve problems are illustrated by the results of field measurements carried out on the shelf of Posiet Bay in the Sea of Japan.

CMOS IC Solutions for the 77 GHz Radar Sensor in Automotive Applications

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology.

HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis

Modern integrated circuit (IC) design incorporates the usage of proprietary computer-aided design (CAD) software and integration of third-party hardware intellectual property (IP) cores. Subsequently, the fabrication process for the design takes place in untrustworthy offshore foundries that raises concerns regarding security and reliability. Hardware Trojans (HTs) are difficult to detect malicious modifications to IC that constitute a major threat, which if undetected prior to deployment, can lead to catastrophic functional failures or the unauthorized leakage of confidential information. Apart from the risks posed by rogue human agents, recent studies have shown that high-level synthesis (HLS) CAD software can serve as a potent attack vector for inserting Hardware Trojans (HTs). In this paper, we introduce a novel automated attack vector, which we term “HLS-IRT”, by inserting HT in the register transfer logic (RTL) description of circuits generated during a HLS based IC design flow, by directly modifying the compiler-generated intermediate representation (IR) corresponding to the design. We demonstrate the attack using a design and implementation flow based on the open-source Bambu HLS software and Xilinx FPGA, on several hardware accelerators spanning different application domains. Our results show that the resulting HTs are surreptitious and effective, while incurring minimal design overhead. We also propose a novel detection scheme for HLS-IRT, since existing techniques are found to be inadequate to detect the proposed HTs.

Rapid time-domain simulation of fractional capacitors with SPICE

Fractional capacitors, commonly called constant-phase elements or CPEs, are used in modeling and control applications, for example, for rechargeable batteries. Unfortunately, they are not natively supported in the well-used circuit simulator SPICE. This manuscript presents and demonstrates a modeling approach that allows users to incorporate these elements in circuits and model the response in the time domain. The novelty is that we implement for the first time a particular configuration of RC elements in parallel in a Foster-type network with SPICE in order to simulate a constant-phase element across a defined frequency range. We demonstrate that the circuit produces the required impedance spectrum in the frequency domain, and shows a power-law voltage response to a step change in current in the time domain, consistent with theory, and is able to reproduce the experimental voltage response to a complicated current profile in the time domain. The error depends on the chosen frequency limits and the number of RC branches, in addition to very small SPICE numerical errors. We are able to define an optimum circuit description that minimizes error while maintaining a short computation time. The scientific value is that the work permits rapid and accurate evaluation of the response of CPEs in the time domain, faster than other methods, using open source tools.

Compilation of Hierarchical Transistor Circuits in SPICE Format

Software tools for compiling and decompiling descriptions of transistor circuits are widely used in computer-aided VLSI design. These two operations are inverse to each other in terms of guiding the design process. Netlist compiling a hierarchical schematics allows its specification to be converted into a functionally equivalent flat netlist. The goal of the decompilation is to reconstruct the hierarchical description of the circuit by extracting subcircuits that are gates or more complex elements. This paper examines the problem of compiling hierarchical MOS transistor circuits. The initial hierarchical schematic and resulting flat netlist are specified in SPICE format. A fast recursive algorithm for compilation of hierarchical descriptions of arbitrary nesting depth and its software implementation in C++ are proposed. During the compilation process, the ports of the circuit substituted in place of the component being compiled are renamed, as well as the names of internal nets and elements in the description of the circuit itself by adding a prefix to them that specifies the path in the hierarchy to the component being compiled. The developed compilation program was tested on a number of practical hierarchical transistor circuits as part of a transistor circuit analyzer for functional equivalence. The results of the compilation program tests make it possible to evaluate the increase in compilation time with increasing complexity of circuits and the depth of subcircuits nesting, as well as to compare the performance of the compilation procedure and its inverse procedure of decompiling the resulting flat netlist.

The Development of a 2D Numerical Model of a Device Using the Elastocaloric Effect to Cool Electronic Circuits

The scientific community has been working hard lately to develop fresh, environmentally friendly refrigeration technologies. Those based on solid-state refrigerants are among the Not-In-Kind Refrigeration Technologies that show great promises. The one based on the elastoCaloric Effect is among the most interesting of them. This paper presents the development of a 2D numerical model for a device harnessing the elastocaloric effect with the primary objective of cooling electronic circuits. The study focuses on the intricate interplay between mechanical and thermal aspects, capturing the dynamic behavior of the elastocaloric material in response to cyclic mechanical loading. The numerical model incorporates detailed descriptions of the electronic circuits, accounting for heat dissipation and thermal management. Through simulations, the optimal configuration for efficient cooling is explored, considering various operative conditions and mechanical loading conditions (tensile and bending). The findings contribute to the advancement of elastocaloric cooling technology, offering insights into the design and optimization of devices aimed at enhancing electronic circuit performance through effective thermal control. The results that the most promising configuration is based on bending, a design choice resulting appropriate for cooling the electronic circuits.

TECHNICAL ADVANTAGE OF BI-CURRENT SYSTEM OF DISTRIBUTED GENERATION

The paper discusses two circuit types of a distributed generation system for supplying power energy to private households. The first of them is called a mono-current system and it is a combined distributed generation system based on solar panels and a wind generator with power supply to AC loads. The second is called a bi-current system because it has two separate power distribution systems for AC and DC. The paper provides their functional and circuit descriptions, as well as a qualitative comparative analysis. The main goal of the work is to prove the technical advantage of the bi-current system. This problem is solved using the method of relative comparative estimates. The number of transformation elements and the generalized efficiency of the power circuit were selected as comparison criteria. As you know, for any system the cost is higher and reliability is lower, than its number of elements is more. It has been defined that during the flow of electrical power from sources to loads in a bi-current system, in general, half as many transformation elements are overcome as in a mono-current system. For any system the operating costs are lower, if the efficiency is higher. When calculating the generalized efficiency, only the power circuit was taken into account, since it is the most power-intensive circuit. The calculation was also performed for a stationary mode close to the nominal one. Such assumptions do not allow us to accurately calculate the quantitative values of efficiency, but they allow us to perform a preliminary qualitative comparative analysis. The paper presents algorithms for calculating the efficiency of both systems. An example calculation showed that the efficiency of the bi-current system is approximately 6% higher. As a result of the research, it was found that the resulting relative estimate of the bi-current system is higher by approximately a quarter of a point, which indicates its clear advantage. Thus, the technical advantage of the bi-current system has been proven, so it is a more promising circuit solution for distributed generation systems.

Spacetime-Efficient Low-Depth Quantum State Preparation with Applications

We propose a novel deterministic method for preparing arbitrary quantum states. When our protocol is compiled into CNOT and arbitrary single-qubit gates, it prepares an N-dimensional state in depth O(log⁡(N)) and spacetime allocation (a metric that accounts for the fact that oftentimes some ancilla qubits need not be active for the entire circuit) O(N), which are both optimal. When compiled into the {H,S,T,CNOT} gate set, we show that it requires asymptotically fewer quantum resources than previous methods. Specifically, it prepares an arbitrary state up to error ϵ with optimal depth of O(log⁡(N)+log⁡(1/ϵ)) and spacetime allocation O(Nlog⁡(log⁡(N)/ϵ)), improving over O(log⁡(N)log⁡(log⁡(N)/ϵ)) and O(Nlog⁡(N/ϵ)), respectively. We illustrate how the reduced spacetime allocation of our protocol enables rapid preparation of many disjoint states with only constant-factor ancilla overhead – O(N) ancilla qubits are reused efficiently to prepare a product state of wN-dimensional states in depth O(w+log⁡(N)) rather than O(wlog⁡(N)), achieving effectively constant depth per state. We highlight several applications where this ability would be useful, including quantum machine learning, Hamiltonian simulation, and solving linear systems of equations. We provide quantum circuit descriptions of our protocol, detailed pseudocode, and gate-level implementation examples using Braket.

Learning by selective plasmid loss for intracellular synthetic classifiers

We propose a learning mechanism for intracellular synthetic genetic classifiers based on the selective elimination (curing) of plasmids bearing parts of the classifier circuit. Our focus is on a two-input, two-plasmid classifier scheme designed to solve a simple proof-of-concept learning problem. The problem is formulated in terms of Boolean variables, and the learning process boils down to selecting the classification rule from three options, given a set of training examples. We begin with a Boolean description of the classifier circuit, demonstrating how it implements the required learning algorithm. We then transition to a continuous steady-state model and establish conditions on its parameters to ensure that the learning process and the classifier output correspond to the Boolean description, at least approximately. The approach to intracellular classifier learning presented here essentially relies on two key prerequisites: (i) compatibility among the plasmids constituting the classifier, such that they have independent or weakly interacting copy number control systems, and (ii) conditional elimination mechanism in each plasmid triggered by a signal from the gene network. The feasibility of this approach is supported by recent experimental findings on engineering compatible pairs and triplets of plasmids and controlled selective plasmid curing. While learning by plasmid loss has certain limitations in universality, we anticipate that it provides greater persistence of a trained classifier to internal and external fluctuations and to degradation over time, as compared to alternative intracellular learning mechanisms outlined in the literature, such as based on gene network dynamics or on variable copy numbers of plasmids sharing a common copy number control system.

Evaluation of Contactless Identification Card Immunity against a Current Pulse in an Adjacent Conductor

This paper analyses the possibility of damaging and destroying an identification chip of the Mifare type in a frequently used contactless identification card of size ID-1, following the standard ISO/IEC 7810 (i.e., with dimensions 85.60 × 53.98 × 0.76 mm), using the magnetic field of an adjacent conductor in which a current pulse of a defined shape and amplitude is flowing. For analysis purposes, the nonlinear current–voltage characteristic of the Mifare chip voltage limiter was measured and approximated, and the mutual inductance of the straight conductor and the rectangle coil antenna in the card was calculated. Next, a mathematical analysis was conducted based on the description of the equivalent electrical circuit by the differential equations. The results of the mathematical analysis were verified by a simulation in the free simulation software Micro-Cap 12. The peak value of the current pulse that can damage the Mifare chip was measured by a combination wave generator. Based on these measurements and the chip characteristics, the energy capable of destroying the chip was calculated. The characteristics of chip damage were determined using a comparison of the resonant characteristics of undamaged and damaged RFID cards with Mifare chips.

Comparative Analysis of Microservice and Serverless Technology Building Automatic Design Systems for Calculating the Instability of the Static Mode of Nonlinear Electronic Circuits

Methods for constructing distributed automation systems for circuit design to calculate the instability of the coordinates of the operating points of the static mode of nonlinear electronic circuits were considered. Two-terminal networks of type R and transmission parameters of dependent sources, as well as characteristicsof external influences (temperature, radiation, etc.) are taken as components that change under the influence of external factors. To solve the problem of calculating the instability of the coordinates of the operating points of the static mode of nonlinear electronic circuits, a technique is proposed based on the use of an auxiliary circuit, which is constructed by transposing the description of the original circuit. The features of the organization of serverless and microservice architecture for building circuit design automation systems are analyzed. The multitenant design of a microservice information system environment is described. The mechanismof operation of the service as a service is presented to ensure the operation of the business logic of the server component.