Compilation of Hierarchical Transistor Circuits in SPICE Format

Abstract

Software tools for compiling and decompiling descriptions of transistor circuits are widely used in computer-aided VLSI design. These two operations are inverse to each other in terms of guiding the design process. Netlist compiling a hierarchical schematics allows its specification to be converted into a functionally equivalent flat netlist. The goal of the decompilation is to reconstruct the hierarchical description of the circuit by extracting subcircuits that are gates or more complex elements. This paper examines the problem of compiling hierarchical MOS transistor circuits. The initial hierarchical schematic and resulting flat netlist are specified in SPICE format. A fast recursive algorithm for compilation of hierarchical descriptions of arbitrary nesting depth and its software implementation in C++ are proposed. During the compilation process, the ports of the circuit substituted in place of the component being compiled are renamed, as well as the names of internal nets and elements in the description of the circuit itself by adding a prefix to them that specifies the path in the hierarchy to the component being compiled. The developed compilation program was tested on a number of practical hierarchical transistor circuits as part of a transistor circuit analyzer for functional equivalence. The results of the compilation program tests make it possible to evaluate the increase in compilation time with increasing complexity of circuits and the depth of subcircuits nesting, as well as to compare the performance of the compilation procedure and its inverse procedure of decompiling the resulting flat netlist.