Derivative Superposition Research Articles

A mm‐wave LNA employing current re‐use and non‐linearity cancellation in 28 nm CMOS for automotive RADAR and 6G receivers

AbstractThis letter reports an 85 GHz low noise amplifier (LNA) employing derivative superposition based non‐linearity cancellation and a current re‐use topology. The LNA employs a two‐stage stacked architecture, each featuring neutralized differential pairs utilizing the same DC current. In derivative superposition, an auxiliary branch consisting of neutralized differential pairs cells is added in the LNA in parallel to stage 1 to ensure non‐linearity cancellation. Layout‐based capacitive neutralization is implemented to improve GMAX, resulting in simplified routing, reduced parasitics, and a more compact layout. The proposed LNA is fabricated in TSMC 28 nm CMOS process and achieves a peak gain of 8.4 dB at 84.2 GHz with a measured 3 dB bandwidth () from 79.4 to 92 GHz. The minimum measured noise figure is 12.8 dB. The LNA draws 34 mA of DC current from a 1.2 V supply. The highly linear LNA with IIP3 +6.5 dBm is tailored for automotive RADAR and 6G receivers.

A 28 GHz Highly Linear Up-Conversion Mixer for 5G Cellular Communications

In this paper, we present a highly linear direct in-phase/quadrature (I/Q) up-conversion mixer for 5G millimeter-wave applications. To enhance the linearity of the mixer, we propose a complementary derivative superposition technique with pre-distortion. The proposed up-conversion mixer consists of a quadrature generator, LO buffer amplifiers, and an I/Q up-conversion mixer core and achieves an output third-order intercept point of 15.7 dBm and an output 1 dB compression point of 2 dBm at 27.6 GHz, while it consumes 15 mW at a supply voltage of 1 V. The conversion gain is 11.4 dB and the LO leakage and image rejection ratio are −56 dBc and 61 dB, respectively, in the measurement. The proposed I/Q up-conversion mixer is suitable for 5G cellular communication systems.

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

Nonlinear Capacitance Compensation Technique in a Linearity-Enhanced and Broadband GaN PA MMIC for Ku-/K-Band Applications

This article reports on exploiting a nonlinear capacitance compensation technique to achieve high linearity for power amplifier (PA) designs in III–V semiconductor technologies. High linearity is achieved by implementing multiple transistors with deliberate sizes and biasing to compensate for each nonlinear input capacitance behavior. Therefore, the composed PA core acts as one large device where each subdevice is biased individually. Moreover, this approach proves to be a reliable and easy way to improve PA linearity in III–V semiconductor technologies. The viability of this compensation is demonstrated by comparing it to other analog linearity improvement techniques such as derivative superposition. As a proof-of-concept prototype, a 17.2–20.2-GHz class-AB PA is designed in a space-evaluated 150-nm gallium nitride (GaN)-on-silicon carbide (SiC) process. Its capabilities are validated for various modulation bandwidths up to 500 MHz at several frequencies while delivering 32 dBm of output power. The measured third-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_3$</tex-math> </inline-formula> ) and the fifth-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_5$</tex-math> </inline-formula> ) are improved by 18 and 25 dB, respectively, compared to a class-AB design. The measured amplitude-to-phase (AM–PM) distortion of less than 0.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> is obtained over the entire bandwidth. Finally, noise-to-power ratio (NPR) results prove the linearity enhancement concept with values better than 15 dB up to maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\rm out}$</tex-math> </inline-formula> . All the results were measured without any applied digital predistortion (DPD).

Linearity Performance of Derivative Superposition in GaN HEMTs: A Device-to-Circuit Perspective

A significant disconnect exists between the linearity metrics used by device and circuit engineers, degrading the maximum achievable performance in gallium nitride (GaN) technology. A detailed linearity analysis is performed using both device and circuit metrics on GaN devices that employ derivative superposition (DS) to evaluate the amplifier performance under modulated conditions of four different device variants. The limitations of conventional linearity metrics used at the device level, such as the output third-order intercept point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{OI}\text{P}_{\text{3}}$</tex-math> </inline-formula> ) and output 1-dB compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{OP}_{\text{1}~\text{dB}}$</tex-math> </inline-formula> ), are examined and compared with communication standard-based metrics, such as the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) to provide best practices for quantifying power amplifier (PA) linearity. It is found that employing more devices in the context of DS primarily improves the input-bias range of the device and not the peak amplifier performance under modulation. Ultimately, this work provides device engineers with a circuit-level perspective on linearity to help design transistors with enhanced RF performance for practical real-world deployment.

A Novel High-Linearity Uwb-Lna Based on Post Distortion and Complementary Derivative Superposition Techniques

A Novel High-Linearity Uwb-Lna Based on Post Distortion and Complementary Derivative Superposition Techniques

A two stage cascode LNA using modified derivative superposition technique in [formula omitted] HBT with an IIP3 of 2 dBm and NF of 4.8 dB for IEEE 802.11ad standard

A two stage cascode Low Noise Amplifier (LNA) is designed in 130 nm SiGe HBT. The work focuses on achieving a low Noise Figure (NF), high linearity, and high gain for the LNA in the frequency band of 57.24 GHz-65.88 GHz to be operated in all the four channels of IEEE 802.11ad standard. A modified Derivative SuperPosition technique is used in the first stage of the cascaded LNA to improve the linearity of the circuit. Post layout Electromagnetic (EM) simulation results of the proposed LNA achieves a peak gain of 20.19dB at 59.5GHz, linearity (IIP3) of 2dBm at the maximum gain and also achieved a NF of 4.1dB - 4.8dB in the operating band of frequency. DC power consumption of the proposed circuit is 9.2mW from a supply voltage of 1.2V, with an area occupancy of 311μm×298μm.

A +7.6 dBm IIP3 2.4-GHz Double-Balanced Mixer With 10.5 dB NF in 65-nm CMOS

In this brief, an enhanced derivative superposition (DS) method is proposed to increase the third-order input intercept point (IIP3) of double-balanced CMOS active mixers. In the proposed mixer, an auxiliary common-gate transconductor biased in the moderate inversion region with a source inductive degeneration is used in the feedforward AC-coupled path to the main transconductor to generate the third-order intermodulation distortion (IMD3) current. Hence, the overall IMD3 current of the transconductance stage is minimized while optimizing the conversion gain (CG). This auxiliary transconductor also improves the overall NF of the mixer by partially cancelling the output noise voltage. In addition, the current reuse and current bleeding techniques are utilized to further improve the overall performance. As a proof-of-concept, a 2.4-GHz down-conversion mixer with an output bandwidth of 10 MHz is implemented in a 65-nm CMOS process. Measurement results show that the mixer achieves a peak CG of 12.5 dB, a double-sideband (DSB) noise figure (NF) of 10.5 dB, and IIP3 of +7.6 dBm. The circuit consumes 1.2 mW from a 1-V supply and excluding the pads, it occupies a silicon area of 0.2208 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications.

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm.

A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB–LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S11 less than −10 dB in the entire 3.1–10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are + 3.84 dBm and + 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm × 1075 mm, including the supply and ESD ring and the pads.

A 0.3–6 ​GHz noise and distortion cancelling LNA achieving an NF of 2.8±0.3 ​dB in 0.18-μm SiGe BiCMOS process

This paper presents a noise and distortion cancelling wideband low-noise amplifier (LNA) in JAZZ 0.18-μm SiGe BiCMOS process. In the proposed design, a shunt feedback (SFB) and a common-emitter (CE) paths are adopted to reduce the dominant noise contribution of the main path. To enhance the linearity, the derivative superposition method is modified to eliminate the whole nonlinearity components. Moreover, with the help of an n-type MOS acted as a resistive load of the CE path, both flat gain and acceptable output impedance matching are achieved. The measurement results exhibit that the LNA has an input third-order intercept point (IIP3) of −4 dBm with a noise figure (NF) of 2.8 ​± ​0.3 ​dB and a power gain 16.5 ​± ​0.2 ​dB from 0.3 to 6 ​GHz. The circuit draws 14.5 ​mA dc current from a 3.3 ​V supply for core area of 0.22 ​mm2.

A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

APPLYING THE DERIVATIVE SUPER POSITION METHOD FOR A HIGH LINEAR COMMON SOURCE CMOS POWER AMPLIFIER IN ULTRA-WIDEBAND APPLICATIONS

The problem with the power amplifiers is that raising the gain and output power may affect the other amplifier factors specially in the frequency ultra-band. This paper presents a CMOS power amplifier (PA) for Ultra-Wideband (UWB) applications in 2.2 to 5 GHz using two stages of common source topology with derivative superposition (DS) method. Simulation results show an average power gain of27.2 dB with an input 1dB compression point (1dB-CP) of -14.6 dBm at 3.2 GHz and an output 1dB compression point (1dB-CP) 12.9 dBm. With an input power of 83.8 mW, from a 1.8 V supply, power added efficiency (PAE) is 47.5% at 3.2 GHz with 50Ω load impedance and stability factor is 7.2 at 3.2GHz. The proposed design has been simulated using TSMC 0.18µm technology. The important parameters that define an RF Power Amplifier are: Output Power, Gain, Linearity, Stability, DC supply voltage, Efficiency, Ruggedness. The design results showed high power output without affecting the other amplifier factors. A comparison with the previous research has been done and the comparison is clearly in favor of the present design.

A 0.5 to 6 GHz wideband cascode LNA with enhanced linearity by employing resistive shunt‐shuntfeedback and derivative superposition

AbstractA wideband bipolar low‐noise amplifier (LNA) with enhanced linearity operating in 0.5 to 6 GHz frequency range is proposed in this letter. The LNA design is based on a cascode amplifier with an emitter degeneration RC parallel network and a resistive shunt‐shunt feedback which can improve linearity. The cascode topology in conjunction with the preceding series inductor L is utilized to achieve good wideband input impedance matching, while the wideband output impedance matching is realized by using an emitter follower as a buffer. And the third‐order input intercept point (IIP3) has been improved due to the derivative superposition technique. The wideband LNA presented in this letter was designed and implemented in a JAZZ 0.18 μm SiGe BiCMOS process. The measured results show that from 500 MHz to 6 GHz, the power gain (S21) is 16.5 to 17.1 dB, the noise factor (NF) is 2.7 to 3.3 dB, the current consumption without buffer stage is 12.4 mA at a 3.3 V supply voltage, and the IIP3 is −0.834 dBm at 2 GHz. The chip size is 1.06 × 0.64 mm2.

Highly linear inductorless asymmetric capacitive cross-coupled wideband balun-LNAs

Two Inductorless balun low noise amplifiers (LNAs- LNA1, LNA2) are proposed in this paper to reduce the noise figure (NF) and improve the linearity. They use asymmetric capacitive cross-coupling (A-CCC) and auxiliary CS amplifier to reduce the NF. Robust derivative superposition is used in LNA2 to improve the 3rd order input intercept point, and hence the linearity. The proposed A-CCC balun-LNAs are implemented in 0.18 µm CMOS technology, and their performances are evaluated through post-layout simulations, PVT variation analysis and Monte Carlo simulations. From these studies, the average NF, gain and the 3dB-bandwidths of LNA1 and LNA2 obtained are (2.49 dB, 20 dB, 0.1–2.48 GHz) and (2.61 dB, 19.8 dB, 0.1–2.0 GHz) respectively. For a 1.2 V supply and an area of 0.02mm2, the power consumption of LNA1 and LNA2 are 4.9 mW and 5.8 mW, respectively. The performances of the proposed LNAs are also compared with other wideband LNAs reported in the literature.

1.2 V asymmetric-CCC based sub-3 dB NF high IIP3 linearity wideband balun-LNA

A CG-CS wideband balun-LNA using asymmetric capacitive cross-coupling (A-CCC) and an auxiliary current reuse amplifier (ACRA) is reported in the literature. It achieves low noise figure (NF) and high gain at the cost of linearity. To improve the linearity, inductive loads are proposed. However, this is at the cost of increase in chip area. To overcome this problem, a balun-LNA using modified complementary derivative superposition and asymmetric CCC-DS techniques for the ACRA and A-CCC block respectively is proposed in this paper. It dispenses with the inductive loads. The balun-LNAs with and without the proposed linearization are implemented in UMC 180 nm CMOS technology with a supply of 1.2 V and are studied through post-layout simulations. It is found that the proposed LNA has +7.96 dBm increase in average IIP3 compared to the LNA without the proposed linearization. It achieves an average IIP3 of +5.49 dBm with a peak gain of 24.2 dB and minimum NF of 2.18 dB over the bandwidth of 1–3 GHz. The proposed LNA requires an area of 0.3 mm2 and a power of 6.95 mW.

A 45–2500-MHz Push–Pull Driver PA With Cross Coupled and Negative Feedback Technique

Derivative superposition technique (DST) is a common linearization technology for designing driver power amplifier (DPA). However, the performance of DST is sensitive to frequency variation. This letter presents a method to improve the 1-dB bandwidth of the DST. The negative feedback resistance (NFR) and cross-coupled capacitance (CCC) are combined with DST as the core of DPA which is applied to a 45–2500-MHz wireless transmitter. The DPA implements a good performance in the measured 193% relative bandwidth. The linearity is measured with 1-dB compressed output power from 9 to 10.2 dBm and the third-order intermodulation less than −37.23-dBc over the whole frequency band. The overall die area of the PA is 0.044 mm2 at TSMC 180-nm technology process, and it draws 22.8 mA from the 1.8-V supply voltage.

A 0.1–2.75 GHz high-linear low-noise transconductance amplifier for high-performance multi-standard wireless applications

The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply.

A 28-GHz CMOS Down-conversion Mixer with Low-magnetic-coupled Source Degeneration Inductors for 5G Applications

This paper presents a 28-GHz CMOS millimeter-wave down-conversion mixer employing a derivative superposition linearization technique with our proposed low-coupling source degeneration inductors for 5G cellular communication systems to improve the linearity performance of the downconversion mixer. The proposed low-magneticcoupled source degeneration inductors avoid the linearity degradation gap between the schematic design without considering magnetic coupling and the post-layout design with considering magnetic coupling effect due to the source degeneration inductors. The down-conversion mixer with local oscillator buffer is implemented using a 65-nm CMOS technology, and it draws a 21 mA from a 1-V supply voltage. It achieves a gain of 10.1 dB, noise figure below 10 dB, and third-order output intercept point of 19.3 dBm from 26.5 to 29.5 GHz.

Low power active shunt feedback CMOS low noise amplifier for wideband wireless systems

This paper presents a wideband low-noise amplifier (LNA) based on active shunt feedback to alleviate the trade-off between noise performance and input matching. Low noise and high linearity are achieved by derivative superposition (DS) and complementary derivative superposition (CDS) techniques. Low power is consumed by biasing the transistors in threshold voltage and forward body biasing. With these modified techniques, low noise figure, high linearity, and improved input matching can be attained for 2–8 GHz frequency band. The simulation results of the designed LNA in TSMC RF CMOS 180 nm technology show the maximum power gain of 11 dB with a ripple of ±0.4 dB, noise figure of lower than 3.5 dB over the whole band of 2–8 GHz, maximum IIP2 of +64 dBm and IIP3 of +14 dBm, while dissipating 7 ​mW from a 1.4 ​V supply voltage. It occupies 0.247 ​mm*0.358 ​mm die area.