Interface State Density Dit Research Articles

A study of the impact of in-situ argon plasma treatment before atomic layer deposition of Al2O3 on GaN based metal oxide semiconductor capacitor

The impact of subjecting a n-GaN surface to an in-situ argon plasma in an atomic layer deposition (ALD) tool immediately before deposition of an Al2O3 dielectric film is assessed by frequency dependent evaluation of Al2O3/GaN MOSCAPs. In comparison with a control with no pre-treatment, the use of a 50W argon plasma for 5min reduced hysteresis from 0.25V to 0.07V, frequency dispersion from 0.31V to 0.03V and minimum interface state density (Dit) as determined by the conductance method from 6.8×1012cm−2eV−1 to 5.05×1010cm−2eV−1.

The effects of (NH4)2Sx treatment on n-GaN MOS device with nano-laminated ALD HfAlOx and Ru gate stack

The effects of ammonium poly-sulfide, (NH4)2Sx, treatment on the surface of GaN metal oxide semiconductor (MOS) device with nano-laminated atomic layer deposition (ALD) HfAlOx gate dielectric and Ru gate electrode were investigated and compared with HCl pre-treatment. Compared with sample without sulfur (S) passivation, S-passivated sample shows improved surface roughness, increased capacitance, higher breakdown voltage, smaller frequency dependence, lower interface state density (Dit). It is found that (NH4)2Sx can remove native oxide and passivate the surface and interface states. Surface oxidation is suppressed due to higher strength in the NS bonds than that of the NO bonds. Further improvement is observed with increasing (NH4)2Sx treatment time.

Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new AlYO3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) AlYO3/Ge MOS structures with plasma post oxidation (PPO). Reduction in Dit by PPO is found for AlYO3/Ge system. A 1.5-nm-thick AlYO3/GeOx/Ge interface with 1.25-nm EOT can provide a lower amount of the slow trap density, particularly in the valence band side of Ge, than the control Al2O3/GeOx/Ge interface and the Y2O3/GeOx/Ge interface. Deposition of any high-k films on the AlYO3/GeOx/Ge structure leads to the increase in the slow trap density to the same level, suggesting the influence of any traps at the interface between the high-k films and AlYO3.

Electrical characteristics of ALD La2O3 capping layers using different lanthanum precursors in MOS devices with ALD HfO2, HfSiOx, and HfSiON gate dielectrics

We have investigated the electrical characteristics – flat band voltage (VFB) shift, equivalent oxide thickness (EOT) scaling and charge trapping – of atomic layer deposition (ALD) La2O3 capped high-k gate dielectrics (HfO2, HfSiOx, and HfSiON) in the metal-oxide-semiconductor (MOS) device structure, where two different lanthanum precursors – ① lanthanum formamidinate, La(fAMD)3, and ② lanthanum betadiketonate, La(thd)3, – were used for ALD capping layer. Regardless of precursors, La2O3 capping layer on the ALD high-k films leads to negative VFB shift and thinner EOT as increasing capping thickness. However, more shift and further EOT scaling are observed with La2O3 thin film using La(fAMD)3. In addition, La2O3 capping layer using La(fAMD)3 precursor shows lower interface state density (Dit) and stronger immunity against charge trapping than La2O3 capping layer with La(thd)3 precursor. Similar trends are attained with Si containing HfO2 – HfSiOx and HfSiON, but amount of VFB shift and EOT reduction is smaller than that of HfO2-based device, resulting from suppressed La-diffusion due to stronger Si–O bonds as well as nitrogen blocking in the dielectrics.

Remote plasma atomic layer deposited Al2O3 4H SiC MOS capacitor with remote H2 plasma passivation and post metallization annealing

Hydrogen (H2) plasma treatment at the interface between 4H-SiC substrate and Al2O3 dielectric prepared by the atomic layer deposition (ALD) was performed and its effects on capacitance–voltage characteristics as well as the interface state density (Dit) was evaluated with metal oxide semiconductor devices. The atomic force microscopy result indicates that the remote H2 plasma treatment reduces surface roughness. Compared with the non-passivated devices, lower leakage current, lower hysteresis and higher breakdown voltage are attained with remotely hydrogen plasma-treated devices. Without post metallization annealing (PMA), Dit value more than 1014eV−1cm−2 is attained with hydrogen plasma passivated devices, indicating plasma-induced damage on the surface. However, using PMA, Dit of the H2 plasma treated device is significantly reduced to as low as 1.00×1012eV−1cm−2 at Ec−Et=0.4eV and is about five times lower than that of sample without H2 plasma passivation (Dit=4.84×1012eV−1cm−2).

Effects of post-annealing on the passivation interface characteristics of AlGaN/GaN high electron mobility transistors

We examined the effects of post-annealing in forming-gas ambient on the spin-on-dielectric (SOD)-buffered passivation as well as the conventional plasma-enhanced chemical vapor deposition (PECVD) Si3N4 passivation structure in association with the quantitative analysis of defects at the passivation interfaces of AlGaN/GaN high electron mobility transistors (HEMTs). Before the annealing, the interface state densities (Dit) of the PECVD Si3N4 are one-order higher (1012–1013cm−2eV−1) than those of the SOD SiOx (1011–1012cm−2eV−1) as derived from C–V characterization. Clear reduction in Dit from the PECVD Si3N4 is extracted to a level of 1011–1012cm−2eV−1 with a stronger absorption from Si–N peak in Fourier transform infrared spectroscopy spectra after the post-annealing. On the other hand, negligible difference in Dit value is obtained from the SOD SiOx. In this paper we propose that much lower measurement levels (~156mA/mm) before the annealing and substantial recovery (~13% increase) after the annealing in maximum drain current density of the AlGaN/GaN HEMTs with Si3N4 passivations are due to the original higher density before the annealing and greater reduction in Dit of the PECVD Si3N4 after the annealing. Significant reduction after the annealing in gate–drain leakage current (from ~10−3 to ~10−5A, 100-μm gate width) of the HEMTs with the Si3N4 passivation is also supposed to be attributed to the reduction of Dit.

A comparative study of atomic layer deposition of Al2O3 and HfO2 on AlGaN/GaN

The atomic layer depositions of Al2O3 and HfO2 on AlGaN/GaN were systematically studied. The band alignments of Al2O3/AlGaN and HfO2/AlGaN were investigated using in situ X-ray photoelectron spectroscopy. A conduction band offset of 1.8 and 1.1 eV were observed for Al2O3/AlGaN and HfO2/AlGaN, respectively. The Al2O3 and HfO2 dielectric layers were found to reduce the leakage current as expected with respect to metal/AlGaN/GaN Schottky diodes, but neither changes the surface states of AlGaN. The positive ionized surface donor states density and average interface state density (D it ) below the AlGaN conduction band edge (0.34 < E C − E T < 0.50 eV), extracted from capacitance voltage (C–V) curves, were ~5 × 1013 cm−2 and 1.1 × 1014 cm−2 eV−1, respectively.

Oxide structure-dependent interfacial layer defects of HfAlO/SiO2/Si stack analyzed by conductance method

This work investigates the interface properties in a metal oxide semiconductor capacitor device with a 3 nm HfAlO/0.5 nm SiO2/Si stacks prepared by various processing conditions. Different Al doping, different postannealing temperatures, and different deposition steps and stacks were considered. Equivalent oxide thickness and flat band voltage (VFB) were obtained from capacitance–voltage measurements. After the measurement, a simple approach was used to correct the error introduced by the series resistance Rs associated with the substrate and contact while carefully monitoring the impact of the tunneling current. The interface state density (Dit) was calculated by the conductance method, and it was observed that the Dit is dependent on the structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit (2.76×1011 eV−1cm−2) whereas tetragonal HfO2 has the highest Dit (1.27×1012 eV−1cm−2). The Dit values of other structures are within the range of observed highest and lowest values.

Electrical Characteristics of RF Sputtered ZnO/HfO2 Interfaces in Transparent Thin Film Transistors

ABSTRACTIn this work, we have reported the interface characterization of rf sputtered ZnO/HfO2 in thin film transistor structure by dc current-voltage and admittance spectroscopy. The interface state density (Dit) of 1013 eV−1cm−2 was extracted from the Gp/ω vs ω plot was comparable to value obtained from the subthreshold behavior. The grain boundary trap density (NGB) of 9.12×1012 cm−2 was estimated using Levinson’s model. The interface state density distribution below the conduction band edge shows a decreasing trend with energy below the conduction band edge. We also studied the impact of introducing MgO interfacial layer between ZnO and HfO2 interface as an approach towards decreasing the interface state density.

Investigation of diode parameters using I–V and C–V characteristics of Al/maleic anhydride (MA)/p-Si structure

Al/maleic anhydride (MA)/p-Si metal–polymer–semiconductor (MPS) structures were prepared on p-Si substrate by spin coating. Device parameters of Al/MA/p-Si structure have been determined by means of capacitance–voltage (C–V) and conductance–voltage (G–V) measurements between 700 kHz and 1⋅5 MHz and current–voltage (I–V) measurements at 300 K. The parameters of diode such as the ideality factor, series resistance, barrier height (BH) and flat band barrier height were calculated from the forward bias I–V characteristics. The investigation of interface states that density and series resistance from C–V and G–V characteristics in Al/MA/p-Si device has been reported. The frequency dependence of the capacitance could be attributed to trapping states. Several important device parameters such as the BH ϕb, fermi energy (EF), diffusion voltage (VD), donor carrier concentration (ND) and space charge layer width (WD) for the device have been obtained between 700 kHz and 1⋅5 MHz. The I–V, C–V-f and G–V-f characteristics confirm that the parameters like the BH, interface state density (Dit) and series resistance (Rs) of the diode are strongly dependent on the electrical parameters in the MPS structures.

Effect of sputtering power on the performance of p-Ni1−xO:Li/n-Si heterojunction solar cells

This study investigates the effects of sputtering power on the performance of p-Ni1−xO:Li/n-Si heterojunction solar cells (HJSCs). The results of this study indicate a strong dependence of the cell characteristics on the sputtering power. Extremely high or low sputtering power generates higher interface state density (D it ), resulting in the lowering of open circuit voltage (V oc ) and fill factor (FF). The cell fabricated at a sputtering power of 100 W has the lowest D it of 7.08 × 1011 cm−2 eV−1, corresponding to the highest conversion efficiency (η) of 4.30 % [short circuit current density (J sc ): 18.06 mA cm−2, V oc : 390 mV, FF: 61.1 %, series resistance (R s ): 4.3 Ωcm2 and shunt resistance (R sh ): 478.75 Ωcm2]. Furthermore, the cell exhibits a considerably poor temperature coefficient of −0.70 %/ °C (J sc : +0.07 %/°C, V oc : −0.52 %/°C and FF: −0.29 %/°C) when compared with conventional solar cells. Further improvement in the D it of the cell is highly imperative for developing p-Ni1−xO:Li/n-Si HJSCs with a high conversion efficiency and a good temperature coefficient.

Effect of Al Doping on the Reliability of ALD HfO2

This work has demonstrated a high quality HfO2 based gate stack by depositing atomic layer deposited (ALD) HfAlOx along with HfO2 in a layered structure. In order to get multifold enhancement of the gate stack quality both Al percentage and distribution were observed by varying the HfAlOx layer thickness and it was found that < 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in average EOT along with up to six fold reduction in gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increased the interface state density (Dit). When devices were stressed in the gate injection mode at a constant field stress dielectrics with Al/(Hf+Al)% ~ 2% showed resistance to stress induced flat-band voltage shift (DVFB), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics of these devices showed a reduced charge to breakdown and an increase in the extracted Weibull slope (β) that further confirms an enhanced dielectric reliability.

Angle-Resolved Photoelectron Spectroscopy Studies of Initial Stage of Oxidation on C-Face 4H-SiC

The practical use of power devices that use SiC has already been reported. However, performance of a SiC MOSFET has not reached the level predicted based on the physical properties of SiC. One of the reasons is that interface state density (Dit) at SiO2/SiC is more than an order of magnitude higher than that at SiO2/Si. Therefore, the reduction of the Dit is important for device performance improvement. Many studies have been performed to reveal the origin of Dit. [1] Also some types of interface defects have been identified, such as carbon clusters, Si/C dangling bonds, and silicon oxycarbides (SiOxCy) species. [2] However, the chemical structure of the interface transition region still remains unclear, resulting in the insufficient understanding of the origin of Dit and the atomic structure of SiO2/SiC interface. Therefore, it is possible to reveal the formation process of SiO2/SiC interface structure by oxidation, to control the interface structure on the basis of the knowledge, the key for improving the performance of the SiC MOSFET. In this paper, we report the results of an examination of the changes in chemical bonding state of SiO2/SiC structure with the progress of thermal oxidation using angle-resolved X-ray photoelectron spectroscopy (AR-XPS). 4H-SiC C-face epitaxial films with 4° off-oriented were used in this study. The samples were prepared as follows. The sample was cleaned in the mixture of H2SO4 and H2O2 (H2SO4:H2O2=4:1) at 80-85 ºC, and the native oxide was removed by dipping in 5% hydrofluoric acid (HF) followed by a rinse in deionized water. The sample was oxidized at 800 °C in dry oxygen with a pressure of 133 Pa. Then, the sample was oxidized in dry oxygen with a pressure of 133 Pa at 850 °C. The Si 2p, O 1s and C 1s photoelectron spectra, excited by monochromatic AlKα radiation, were measured at a photoelectron take-off angle of 15 and 90 ° with an energy resolution of 0.37 eV and an acceptance angle of 3.3 °, using an ESCA-300 manufactured by Scienta Instruments AB [3]. Figures 1 (a) and (b) show Si 2p and C 1s photoelectron spectra arising from the sample, respectively. Here, these spectra are normalized by Si 2p and C 1s photoelectron intensity arising from SiC substrate. Figures 1 (c), (d) and (e) show the decomposed Si 2p 3/2 and C 1s spectra, respectively. As seen in Fig. 1 (a), the oxide increases with the increase of oxidation time. As seen in Fig. 1 (b), components present in the unoxidized sample is reduced by the oxidation. The measured spectra in Si 2p and C 1s regions were also decomposed into peaks superposition of Gaussian and Lorentzian as shown in Figs. 1 (c), (d) and (e). [4] Figure 2 shows the oxidation time dependence of oxide thickness. As seen in Fig. 2, the oxidation rate decreases at the oxide thickness of 0.9nm and 1.5nm (Δt = 0.6nm). This implies that the oxidation rate is changed to reflect the crystal structure.Acknowledgments This work was partly supported by the MEXT-Supported Program for the Strategic Research Foundation at Private Universities 2009-2013, and by the Strategic Information and Communications R&D Promotion Programme (SCOPE) from MIC, Japan.[1] T. Zheleva, et al., APL. 93, 022108 (2008).[2] Q. Zhu, et al., APL. 99, 082102 (2011).[3] U. Gelius, et al., J. Electron Spectrosc. Rel. Phen. 52, 327 (1990).[4]H. Okada, et al., ECS Transactions, 50 (3) 243 (2012)

Control of 4H-SiC (0001) Thermal Oxidation Process for Reduction of Interface State Density

1. Introduction Thermally-grown oxides on SiC have been considered to induce significant amount of interface defects and near-interface traps, which limit the electron mobility of SiC-MOSFETs. Since the carbon residues are the most possible origin of those defects [1], it is crucial to employ preferred oxidation conditions for the smooth CO desorption. In this study we demonstrate the formation of SiC MOS interface with reduced interface state density (Dit ) <1011 cm-2eV-1, simply by the control of thermal oxidation conditions. 2. Reactions of SiC -O2 System If we assume a reaction with non-equilibrium state where the products are immediately removed away, the reaction with the most negative free energy change would be thermodynamically preferred among the possible reactions. The ideal reaction, SiC+3/2O2→SiO2+CO where the SiO2 formation is accompanied with the direct ejection of CO molecule from SiC, is predicted to be dominant only in the limited range of temperature for a given O2 pressure. This is because carbon precipitation (SiC+O2→SiO2+C) will dominate for low temperature region, whereas oxygen vacancy formation (SiC+O2→SiO+CO) will be significant for high temperature region [2]. The temperature window for the ideal reaction in 1-atm-O2 is estimated to be around 1100oC – 1300oC, if we take account of the solubility of O2 in SiO2, ~ 2.5×1016 cm-3[3]. Actually, we have observed a high activation energy of the growth rate on 4H-SiC (0001) for these conditions [4], which is in good agreement with the calculated energy barrier for the direct CO ejection from the interface [5]. 3. Nearly-ideal MOS C haracteristics on SiC 4H-SiC (0001) wafers, with ~1×1016 cm-3 n-doped epitaxial layers, were oxidized at 1100 and 1300oC in 1-atm O2 ambient to grow ~14 nm SiO2. A ramp furnace with a short rise/fall time was employed, to demonstrate the oxidation only within the preferred temperature range, by minimizing the unwanted additional oxidation at low temperature. The C-V characteristics of the MOS capacitor are shown in Fig. 1, together with an ideal C-V curve given by Poisson’s equation. The good agreement indicates a successful formation of the interface with very low interface defect density. Especially, the nearly-ideal behavior in accumulation region indicates a suppression of border-trap formation in near-interface oxide [1].The Dit values estimated by the conductance method at 150 – 300 K were around 1011 cm-2eV-1 or less, for the energy range 0.1 – 0.4 eV below the conduction band, as shown in Fig. 2. Both 1100oC and 1300oC oxidations result in similar Dit , however, it should be noted that the best results were demonstrated by applying the low-temperature post-oxidation annealing at 800oC in 1-atm O2 where Dit was reduced to less than 1011 cm-2eV-1 even 0.1 eV below the conduction band edge. This temperature is sufficiently low to neglect the additional oxidation of SiC, but expected to annihilate the oxygen vacancies [6] induced by high-temperature oxidation. These Dit values are even less than the best reported ones with P-passivated interface [7]. 4. Conclusions We demonstrated nearly-ideal MOS characteristics on 4H-SiC (0001) with low interface state density <1011cm-2eV-1simply by the control of thermal oxidation conditions, without applying any additional passivation techniques.

High Electron Mobility n-Channel Ge MOSFETs with Sub-Nm EOT

1. Introduction The demonstration of high electron mobility in Ge n-MOSFETs is not an easy task due to unknown carrier scatterings in Ge inversion channel. The first step to clear the big hurdle is to improve the peak electron mobility by reducing the interface states density (Dit ). We have succeeded in the reduction of Dit (<1011 eV-1cm-2) at Ge/GeO2 interface by employing the high-pressure O2 oxidation (HPO) [1, 2]. However, there still remain two critical challenges. One is how to suppress the significant degradation of high-Ns electron mobility (Ns: carrier density). The other one is how to keep high electron mobility in the thin EOT region [3]. Those two are of paramount importance for pushing Ge CMOS in the real technology. 2. Reinvestigation of High-Ns Electron Mobility Coulomb scattering, phonon scattering, and surface roughness scattering are generally considered in MOS inversion layer. By employing HPO, Coulomb scattering has been dramatically reduced, resulting that the peak electron mobility in Ge n-FET is now x2.5 higher than that in Si case [1]. On the other hand, high-Nselectron mobility is generally understood from the interface roughness scattering. Here, not only the roughness height but also the roughness correlation length should be considered, according to the conventional roughness scattering theory [4, 5]. First, we have challenged to realize the atomically flat Ge (111) surface by using H2annealing [6] to reduce the roughness correlation length.Next, it is discussed how the atomically flat surface is affected by the oxidation. The results show that the step and terrace structure is maintained by selecting the temperature under a high-pressure oxidation [7].Then, excellent high-Nselectron mobility has been demonstrated. 3. EOT Reduction Recently we have newly found two facts to breakthrough this challenge. The first one is that the low temperature HPO reduces the oxidation rate [8]. This fact enables us to achieve ~2 nm EOT GeO2 on Ge with superior interface and bulk GeO2. The other one is to replace HPO-GeO2 with high-k oxides which are thermodynamically appropriate for Ge. This means that we can use low oxygen potential oxides instead of HPO- GeO2. Then, we have reached a conclusion that Y2O3 is one of the best candidates on Ge [9]. This material is actually what we have regarded as the Ge-friendly insulator for Ge gate stacks previously from experimental viewpoint [10]. Our recent results have shown that Y2O3-doped GeO2 (YGO) is better than pure Y2O3 on Ge [11]. The resultant electron effective mobility in Ge n-FETs at Ns=1013cm-2is significantly improved down to sub-nm EOT region. Conclusion We can engineer the Ge interface through understanding both of thermodynamics in gate stack formation and of kinetics in surface planarization and oxidation. Thus, it is concluded that Ge CMOS is quite promising. Acknowledgements This work was partly supported by Grant-in-Aid for Scientific Research (A) by Japan Society for the Promotion of Science (JSPS), and by the JSPS Core-to-Core Program “International Collaborative Research Center on Atomically Controlled Processing for Ultra-large Scale Integration” References [1] C. H. Lee et al., TED-58(2011)1295.[2] K. Nagashio et al., MRS Symp. Proc. 1155(2009) C06-02.[3] M. Caymax et al., IEDM 2009-461.[4] Y. Matsumoto and Y. Uemura, JJAP Suppl. 2(1974) 367.[5] C. H. Lee et al., JJAP 51(2012)104203.[6] T. Nishimura et al., APEX 5(2012)121301.[7] C. H. Lee et al., IEDM 2013-32.[8] C. H. Lee et al., APEX 5 (2012)114001.[9] C. H. Lee et al., IEDM 2013-40.[10]A. Toriumi et al., “Advanced Gate Stacks for High-Mobility Semiconductors", pp. 257-267 (2007, Springer).[11] C. Lu et al., APL. 104 (2014) 092909.

In Depth Study of Ge Impact on Advanced SiGe PMOS Transistors

SiGe material brings outstanding advantages for pMOS transistors [1,2]. Low Vt values are much easier to control thanks to specific band structure. The strain induced by engineering of lattice mismatch with silicon leads to enhanced mobility and performances. However a lot remains to understand in these processes and performances. This paper puts the light on two effects: (1) an unexpected Vt shift induced by Ge and (2) the relative impact of Ge, strain and defects on the mobility gain.Many SiGe processes and architectures have been studied to allow clear and reproducible conclusions: (1) pMOS with a given Ge content and various stack thicknesses; (2) pMOS with a given stack and various Ge compositions; (3) SiGe pMOS performed by epitaxy or by Ge-enrichment technique, from unstrained or strained Si substrate, leading to various combinations of stress and Ge content. Both bulk and SOI devices have been processed. Data have been analyzed in a global and coherent view, thus avoiding addressing non pertinent data. Extra Ge-induced Vfb shift: Advanced simulations have been performed using UTOX simulator [3,4]. 6×6 kp simulations and Poisson Schrodinger allow to simulate band structures with strain effects for all %Ge as well as electrical C(V) responses. Comparison between simulations and experiments indicates an extra Vt shift which is not expected from the band structure (Fig.1). This shift is proportional to %Ge content in the channel; it has been observed on SOI and Bulk devices.The analysis of the various gate stack thicknesses rules out an effect of charges in the stacks or at the interfaces. All the electrical data lead to a behavior explained with a Ge induced dipole at the SiGe/SiON interface. Detailed SIMS analysis (Fig.2) as well as STEM, EELS, HAADF experiments show a slight Ge diffusion in SiON probably explaining the dipole at this interface. Notice that this diffusion does not reach the SiON/HfO2 interface and the other existing dipole at this interface [5]. This result is essential for future devices design and modeling, as the extra shift is in the range of the expected Vt (~0.2V). Mobility on strained pMOS: The described processes induce an initial biaxial compressive stress in SiGe layer. This stress improves significantly the channel hole mobility. Meanwhile Ge atoms degrade the SiGe/SiON interface and increase the interface states density Dit (Fig.3). These Dit are related to Ge diffusion in SiON and induce dipoles. However they have no direct effect on Vt.Using the various technological splits available we have compared splits with similar final strain but different concentrations of Ge (Fig.4). This shows that the strain generated by lattice mismatch has a 1storder effect. The percentage of Ge itself as well as generated dipoles and Dit play a minor role, at least at the low %Ge (≤30%). At higher %Ge this is no more true and the gain by strain is counter-balanced by the interface degradation. An improvement of process is required to maintain a good interface quality.Real devices have 10-20 nm length and width. In this case the strain can relaxed depending on directions and may significantly increase or decrease the performances. A careful strain engineering is then expected. This will be discussed in the final paper.

Electrical Characteristics of n, p-In0.53Ga0.47As MOSCAPs With In Situ PEALD-AlN Interfacial Passivation Layer

The effects of plasma enhanced atomic layer deposition (PEALD)-AlN interfacial passivation layer (IPL) on the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As interfaces qualities are studied with different plasma powers. The improvement in electrical properties, including capacitance-voltage (C-V) hysteresis, frequency dispersion, and interface state densities (Dit) are demonstrated on the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /n, p-In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOS capacitors. The excellent C-V behaviors are observed on both type of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As-based MOS devices by performing a thin AlN-IPL at the plasma power of 150 W. To explore the interaction between PEALD-AlN layer and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As surface, X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy analyses have also been characterized.

High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain

In this paper, we report Ge pand n-channel metal- oxide-semiconductor field-effect transistors (MOSFETs) with NiGe source/drain (S/D) with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge junctions were ~10 5 and ~2 × 10 4 at |V| = ±1 V, respectively. Interface state densities Dit of Al 2 O 3 /GeO 2 /Ge stack is improved to be around 10 12 /eV -1 cm 2 near the midgap after forming gas annealing; the gate-stack also shows excellent reliability under constant field stressing. Both p- and n-channel MOSFETs show sufficiently high I ON /I OFF ratio. High driving current of ~9 and ~4 μA/μm at |V GS - V T | = ±0.8 V and |V DS | = ± V is obtained, respectively, for pand n-MOSFETs. Moreover, S/D series resistance R SD of the p- and n-MOSFET is reduced by ~25% and ~42% as compared with that of the transistors with conventional p/n junctions.

High Quality of Ultra-Thin SiO x N y Films Prepared in Nitrous Oxide Ambients Using Thermal Low-Pressure Oxynitridation

The thermal low-pressure oxynitridation of Si(100) in N2O has been studied for ultra-thin (<5 nm) SiO x N y films. The nitrogen concentration and depth profiles were accurately determined by secondary ion mass spectrometry. It has been found that small amounts of nitrogen uniformly distribute in the dielectrics, and the kinetics of the oxynitridation (i.e., thickness vs. time) can be accurately expressed as a logarithmic equation. Meanwhile, the electrical properties of the oxynitride films: the average breakdown equivalent fields of dioxide (EBD), the breakdown time (TBD), the fixed charge (Qf), and the interface state density (Dit) have been characterized and analyzed by the current–voltage (I–V), the time-dependent dielectric breakdown, the capacitance–voltage (C–V), and the conductance–frequency (G–W), respectively. The oxynitride films with EBD ≈ 15.46 MV cm−1 and TBD ≈ 2.39 E4 ms were prepared successfully by processing optimization. The result reveals that the thermal low-pressure oxynitridation is helpful to obtain excellent gate dielectrics with low interface state density (Dit with an order from 2.0 E9 to 3.0 E10 ev−1 cm−2). Such a result can be attributed to nitrogen incorporation and slow growth rate during low-pressure processes. It is concluded that the characteristics of the oxynitride films are suitable for applications in metal-oxide-semiconductor and nonvolatile memory devices.

Importance of Ge surface oxidation with high oxidation rate in obtaining low interface state density at oxide/Ge interfaces

The formation of a gate-insulator/Ge interface with a low interface state density (Dit) starts with oxidation at the Ge surface under appropriate conditions. In this study, a key physical parameter for realizing Dit lower than 1011 eV−1 cm−2 during the oxidation process was clarified by comparison between the experimental results and results calculated based on a proposed model including a time-dependent defect distribution near the Ge-oxide/Ge interface and movement of the interface due to the oxidation at the Ge surface. Dit near the midgap is determined by the competition between the rate of defect creation near the Ge-oxide/Ge interface and the movement rate of the interface, which is the Ge oxidation rate. Oxidation with a Ge oxidation rate of more than 0.1 nm/s can lead to Dit lower than 1011 eV−1 cm−2, taking into account the defect creation rate in a typical Ge device fabrication process, which is 10−2 to 10−4 nm/s.