Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation

Abstract

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new AlYO3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) AlYO3/Ge MOS structures with plasma post oxidation (PPO). Reduction in Dit by PPO is found for AlYO3/Ge system. A 1.5-nm-thick AlYO3/GeOx/Ge interface with 1.25-nm EOT can provide a lower amount of the slow trap density, particularly in the valence band side of Ge, than the control Al2O3/GeOx/Ge interface and the Y2O3/GeOx/Ge interface. Deposition of any high-k films on the AlYO3/GeOx/Ge structure leads to the increase in the slow trap density to the same level, suggesting the influence of any traps at the interface between the high-k films and AlYO3.