Reduction of slow trap density of Al2O3/GeOx/n-Ge MOS interfaces by inserting ultrathin Y2O3 interfacial layers

Abstract

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new Al2O3/ultrathin Y2O3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) Al2O3/Y2O3/Ge MOS structures with plasma post oxidation (PPO) for introducing Y into GeOx and mitigating slow trapping. Both Dit and slow trap density (ΔNst) in the Al2O3/Y2O3/Ge system are reduced by PPO. A 1.5-nm-thick Al2O3/0.63-nm-thick Y2O3/GeOx/Ge interface can provide a 36% lower amount of ΔNst at Eox of 3×106V/cm with maintaining similar levels of Dit than the control Al2O3/GeOx/Ge interface. It is found that the optimum Y2O3 thickness exists for minimizing ΔNst.