Density Of Fast Surface States Research Articles

Effect of Process-Related Impurities on the Electrophysical Parameters of a MOS Transistor

It is established that the electrophysical characteristics of MOS transistors largely depend on the quality of a gate dielectric. The presence of an extra built-in charge in the dielectric and fast surface states at the SiO2/Si interface leads to both an increased threshold voltage and decreased saturation current and voltage, decreased slopes of the characteristics of the MOS transistor in the linear and saturation regions, and a decreased structure conductance in the linear region. The gate leakage currents also increase. It is shown that the view and shape of the capacity–voltage characteristics are determined by the value of an extra positive charge in the bulk of the dielectric and the density of fast surface states at the Si/SiO2 interface. These values are correlated to the profile of the distribution of the surface concentration of the process-related impurities adsorbed at the wafer surface during the manufacturing of the device, which allows us to judge the quality of the materials used, adherence to the production conditions, and, if necessary, correct them opportunely as required.

Effect of annealing on the electrophysical properties of CdTe/HgCdTe passivation interface by the capacitance–voltage characteristics of the metal–insulator–semiconductor structures

The capacitance–voltage characteristics of metal–insulator–semiconductor structures based on Hg1−xCdxTe (x = 0.218) with CdTe passivation are studied before and after the passivation annealing process. We found that after vacuum annealing at 300 °C for 24 h, the micromorphology of the passivation layer was significantly improved, and as the fixed charge density decreased from 1.3 × 1012 cm−2 to 1.0 × 1010 cm−2, the fast surface state density decreased from 2 × 1013 cm−2 eV−1 to 3 × 1012 cm−2 eV−1, with a minimum value of 1.2 × 1011 cm−2 eV−1. From these findings, combined with the secondary ion mass spectroscopy analysis, we conclude that the annealing process propagates an equivalent electrical surface for CdTe/HgCdTe uniformly from the principal physical interface to the inside of the bulk material, effectively improving the characteristics of the CdTe passivation layer.

Electrical characterizations of MIS structures based on variable-gap n(p)-HgCdTe grown by MBE on Si(0 1 3) substrates

Metal–insulator–semiconductor (MIS) structures based on n(p)-Hg1-xCdxTe (x = 0.22–0.40) with near-surface variable-gap layers were grown by the molecular-beam epitaxy (MBE) technique on the Si (0 1 3) substrates. Electrical properties of MIS structures were investigated experimentally at various temperatures (9–77 K) and directions of voltage sweep. The “narrow swing” technique was used to determine the spectra of fast surface states with the exception of hysteresis effects. It is established that the density of fast surface states at the MCT/Al2O3 interface at a minimum does not exceed 3 × 1010 eV−1 × cm−2. For MIS structures based on n-MCT/Si(0 1 3), the differential resistance of the space-charge region in strong inversion mode in the temperature range 50–90 K is limited by the Shockley-Read-Hall generation in the space-charge region.

Interface properties of MIS structures based on hetero-epitaxial graded-gap Hg1-xCdxTe with CdTe interlayer created in situ during MBE growth

Heterostructures based on n-Hg1-xCdxTe (x = 0.23–0.40) with near-surface graded-gap layers were grown by molecular beam epitaxy on Si (013) substrates. At 77 K, the admittance of the In/Al2O3/Hg1-xCdxTe metal-insulator-semiconductor (MIS) structures with grown in situ CdTe intermediate layer and without such a layer was investigated. It has been established that MIS structures of In/Al2O3/Hg1-xCdxTe with an interlayer of in situ grown CdTe are characterized by the electrical strength of the dielectric and the qualitative interface. The hysteresis of the capacitive characteristics is practically absent within a small range of variation in the bias voltage. The density of fast surface states at the minimum does not exceed 2.2 × 1010 eV−1 cm−2. MIS structures of In/Al2O3/Hg1-xCdxTe without an intermediate layer of CdTe have significantly higher densities of fast and slow surface states, as well as lower values of the differential resistance of the space-charge region in the regime of strong inversion.

New mechanism of semiconductor polarization at the interface with an organic insulator

A semiconductor—organic-insulator system with spatially distributed charge is created with a uniquely low density of fast surface states (N ss ) at the interface. A system with N ss ≈ 5 × 1010 cm–2 is obtained for the example of n-Ge and the physical characteristics of the interface are measured for this system with liquid and metal field electrodes. For a system with an organic insulator, the range of variation of the surface potential from enrichment of the space-charge region of the semiconductor to the inversion state is first obtained without changing the mechanism of interaction between the adsorbed layer and the semiconductor surface. The effect of enhanced polarization of the space-charge region of the semiconductor occurs due to a change in the spatial structure of mobile charge in the organic dielectric layer. The system developed in the study opens up technological opportunities for the formation of a new generation of electronic devices based on organic film structures and for experimental modeling of the electronic properties of biological membranes.

Studies on surface processing and passivation of p-Hg1−xCdxTe

A mercury cadmium telluride (MCT) surface subjected to different processing steps of polishing, chemical and electrochemical etching has been examined using x-ray diffraction (XRD). The presence of several oxide phases as well as the elemental tellurium on the substrate surface has been revealed. It is shown that a combination of chemical and in situ electrochemical etching can effectively remove the defective layer containing the oxides as well as the surface tellurium. Cadmium sulfide films grown by a chemical deposition route have been investigated as a passivant for mercury cadmium telluride. The CdS films have been characterized using optical and x-ray diffraction techniques. Frequency-dependent low temperature capacitance measurements of the Au/Hg1−xCdxTe/CdS/Au structure have been used to investigate the electrical properties of the interface. It is shown that the in situ electrochemical etching prior to passivation results in the fabrication of metal–insulator– semiconductor (MIS) devices with low fast and slow surface state density and negligible hysteresis.

The investigation into charge degradation of MIS structures under strong electric field by a method of controlled current load

A new method for studying charge degradation of MIS structures by applying a controlled current load to the structure and taking the time dependence of the voltage is suggested. It allows designers (without switching the structure) to monitor changes in the charge state of MIS structures under the conditions when the capacitance is charged and the charge is injected into the insulator. Charge degradation of metal-PSG-passivated thermal silicon dioxide-insulator structures was studied. It was found that both the SiO2 space charge and the density of fast surface states generated by tunnel electron injection from the SiO2 electrode decrease once current load has disappeared.

The formation of twins in 〈111〉 HgCdTe grown by travelling heater method and their effect on device quality

Hg 1− x Cd x Te crystals with x∼0.2 were grown by the traveling heater method (THM) in either the [111]A or the 1185 [ 1 1 1 ]B directions using oriented CdTe seeds. Lamellar and double position twins are sometimes formed during the growth of these crystals. The lamellar twinning occurs during the layer-by-layer mode of growth, and is due to high stresses originating from high thermal gradients. Double-position (DP) twins develop under multinucleated growth. This type of growth occurs towards the end of the growth run due to the concave shape of the growth interface at that stage. In crystals grown in the [111]A direction, the lamellar twins, of orientation [ 5 1 1 ]B, are constantly growing at the expense of the original [111]A oriented grain. Growth in the [ 1 1 1 ]B direction, on the other hand, suppresses the growth of the lamellar twin domain. The annihilation is due to arrays of small size interstitial A δ+ ions. Ingots grown in the [ 1 1 1 ]B direction are almost entirely single crystalline, with a growth axis of the <111> type. Photodiodes and capacitors realized on the (111)A plane are markedly superior to those on the lamellar twin plane, ( 5 1 1 )B. The difference is due to a much higher fixed charge and larger fast surface state density in the case of the ( 5 1 1 )B plane. These effects are explained by the lattice structures in the {111} and {511} planes and their possible influence on surface reactivity.

The influence of surface states on the photovoltage of real silicon surface

AbstractThe surface photovoltage caused by band‐to‐band generation within the semiconductor depends on light intensity. This dependence differs significantly in two limiting cases. When recombination via fast surface states is negligible, the slope of the photovoltage versus the logarithm of intensity is always less than kT/e and depends on the amount of semiconductor band bending in the dark. When recombination via fast surface states becomes strong, this slope is kT/e, independent of the band bending. These differences are experimentally observed using a structure with ferroelectric NaNO2 deposited on a real silicon surface. The switching of the direction of the spontaneous polarization of the ferroelectric results in significant changes of the semiconductor band bending in the dark. The charge exchange with slow surface states results in a continuous change of the band bending in the dark. The measurements reveal a pronounced minimum of the density of fast surface states near mid‐gap. The results compare well to those from measurements on a field effect transistor structure with NaNO2 as gate insulator.

Degradation mechanisms of gamma irradiated LWIR HgCdTe photovoltaic detectors

Planar n/sup +/p Hg/sub 1-x/ Cd/sub x/Te (x=0.23) photodiodes passivated with ZnS were irradiated by a Co/sup 60/ gamma source. A strong increase in the reverse dark current was observed for doses above 0.3 Mrad(air). A similar effect is found by exposing the photodiodes to UV illumination from a high-pressure mercury lamp. By filtering the UV light it is shown that the degradation in the performance of the photodiodes is caused by the light or radiation absorbed in the ZnS layer above the implanted n-type region. C-V measurements of irradiated MIS devices showed a significant increase in the fast surface state density. Galvanomagnetic and lifetime measurements made on irradiated p-type HgCdTe layer showed no significant changes in the bulk transport parameters. Based on these findings, a model for the degradation mechanism is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of dark current in IR detectors on thinned p-type HgCdTe

A model for the diffusion dark current in MIS IR detectors on thinned bulk p-type HgCdTe is discussed. The model includes trap-assisted tunneling mechanisms in the back-side depletion region as well as the effects of fast surface states. Expressions for the net recombination rate are developed for situations in which trap-assisted tunneling transitions are allowed. Calculations for 12- mu m optical cutoff detectors operating at liquid-nitrogen temperature show that the properties of the back side, including surface fixed charge density, depletion region trap density, fast surface-state density, and majority carrier concentration, have a strong influence on the dark current levels of detectors on thin material. It is predicted that typical as-fabricated surface parameters will not result in large dark current densities. Calculations for detectors with surface parameters common to stressed (degraded) back surfaces, however, show dark current densities which would significantly affect detector performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The characterization of anodic fluoride films on Hg1−xCdxTe and their interfaces

A novel anodic fluoridization process for forming native fluoride films on Hg1−xCdxTe is described. As in the case of the anodic oxide, the anodic fluoride grows in two steps: a dissolution–precipitation step is followed by a bulk growth. Anodic fluorides free of oxygen are grown from nonaqueous solutions. The presence of water causes the growth of films containing both fluorine and oxygen, whereas a low hydroxyl ion concentration causes the growth of anodic oxide alone. However, its electrical behavior is different from that of anodic oxide grown from fluoride‐free baths. The results of Auger electron spectroscopy analysis indicate that the anodic fluoride is composed of cadmium fluoride in a matrix of tellurium, cadmium, and mercury. The fluoride is homogeneous and has a relatively abrupt dielectric–semiconductor interfacial transition, free of contaminants. Metal–insulator–semiconductor devices containing a fluoride film and evaporated ZnS have been fabricated and characterized. By choosing an appropriate ratio of fluoride to hydroxyl ions in the anodization bath the band bending at the n‐type Hg1−xCdxTe surface can be adjusted from near flatband conditions to strong accumulation. Anodization from a nonaqueous solution results in a p‐type Hg1−xCdxTe surface that is slightly depleted due to a fixed charge density of ∼5×1010 cm−2. There is only a negligible density of both slow and fast surface states. Low and reproducible surface state densities are achieved by a short dissolution–precipitation step. Such interfaces are stable up to 105 °C.

The effect of processing conditions on the GaAs/plasma-grown insulator interface

The effect of processing conditions on the interface state density was evaluated from C-V measurements on metal-oxide-semiconductor capacitors. The optimum processing condition for the minimum surface state density was found to be related to the postoxidation annealing temperature and time, and was independent of chemical treatments prior to oxidation. Annealing at the optimum condition (i.e., at 350 °C for 1 h in either nitrogen or hydrogen gas, with or without an aluminum pattern on the oxide) reduces the fast surface state density by about one order of magnitude. By using a nitrogen/oxygen plasma, the static dielectric constant of the oxide decreased as the N/O ratio was increased, and nitrogen was incorporated into the oxide. In addition, the fast surface state density was reduced as a result of this nitridation process.

Interface of p-type Hg1−xCdxTe passivated with native sulfides

The process for forming native sulfide films on p-type Hg1−xCdxTe with x≂0.2–0.3 by anodic sulfidization is described and studied. The analytical, optical, and electrical properties of the resulting interface are reported. The results of Auger electron spectroscopy analysis indicate that homogeneous CdS films with an abrupt interfacial transition are formed on Hg1−xCdxTe with x=0.215–0.290. The measured dispersion of the index of refraction and the dielectric constant of the native sulfide films are consistent with the reported data for bulk CdS. The interface between Hg1−xCdxTe and its native sulfide in combination with deposited ZnS has excellent electrical properties. A low fixed surface state density of the order of Nss ≂5×1010 cm−2, a low concentration of fast surface state density of the order of 5×109 cm−2 eV−1, and a small amount of trapping effects in the sulfide are observed. The MIS capacitors exhibit thermal stability up to 95 °C anneal in vacuum. The main features of the interface of p-HgCdTe utilizing native sulfides are the low fixed surface states and the practically flatband conditions which are imposed for a wide range of composition x and doping level of the substrates. It contrasts with the high fixed positive surface-state density which is observed on interfaces utilizing native oxides of HgCdTe and which invariably invert the surfaces of p-Hg1−xCdxTe. The properties of the interface between Hg1−xCdxTe and its native sulfide suggest potential applications for improving the surface passivation of photovoltaic diodes implemented on p-type Hg1−xCdxTe.

Photoluminescence and x-ray photoelectron spectroscopy measurements of InP surface treated by acid and base solutions

A very strong effect up to three orders of magnitude of chemical treatment on photoluminescence (PL) intensity from InP surface is demonstrated by in situ and ex situ measurements. It is found that InP treatment by acid solutions gives generally high PL intensity, in contrast to the base solutions which give low PL amplitude. Very detrimental effect of H2O2 in H2O and/or in presence of bases is demonstrated. Similar results are obtained in situ, in liquid ambiance and ex situ, immediately after treatment. A reduction of the PL signal is always observed after low-temperature (150 °C) annealing in vacuum (10−6 Torr). Although HF, HNO3, and H2SO4 give similar PL intensity immediately after treatment, a great difference between these treatments becomes apparent after annealing. The amount and nature of oxide layers left by various treatments on In P surface were evaluated by x-ray photoelectron spectroscopy. The average oxide thickness and composition do not seem to be directly correlated with fast surface state density and PL intensity. Our results suggest that InP surface treatment by oxidizing acid solution may be the most promising for device application.

Device-quality SiO 2 films on InP and Si obtained by operating the pyrolytic CVD reactor in the retardation regime

A cold wall atmospheric pressure Chemical Vapor Deposition (CVD) reactor was used to deposit films of SiO 2 at 250°C on n-InP and p-Si substrates. By varying the ratio of oxygen to silane flow rates, the reactor was operated in both the reaction rate controlled and retardation regimes. The insulator-semiconductor interface was evaluated with the aid of high frequency and quasi-static C- V curves. Films deposited on Si in the retardation regime with O 2:SiH 4 = 6 had lowest Q ss of 5.8 × 10 11 cm −2 and minimum fast surface state density of 1 × 10 11 cm −2 eV −1. C- V curves on InP had a hysteresis of 0.5 V, a well defined dip in the quasi-static curve and the accumulation capacitance exhibited no frequency dispersion.

The effect of low pressure plasma on Si–SiO2 structures and GaAs substrates

The degradation of insulating films and GaAs substrates by exposure to low pressure plasma is investigated. In Si–SiO2 structures, the increased density of fast surface states and the nonuniform storage of positive trapped charges within the oxide layer is responsible for the degradation of MOS devices exposed to low pressure plasma. The charge carrier reduction due to the creation of compensating defects during the hydrogen plasma treatment of n-GaAs is reported.

The interface of plasma-anodized Hg1−xCdxTe

The process for forming plasma-anodized oxide on Hg1−xCdxTe with x = 0.215 and 0.290 and the properties of the interface are studied. The results of Auger electron spectroscopy and x-ray photoelectron spectroscopy surface analytical characterization and the electrical interface characterization are compared with respective data on the interface between Hg1−xCdxTe and its solution anodized native oxide. The plasma oxide exhibits a decreasing gradient of oxygen and an increasing gradient of unoxidized tellurium from the surface towards the bulk semiconductor. An accumulation of fluorine at the interface unique to the plasma oxide is observed. Metal-Insulator-Semiconductor (MIS) devices with the plasma-anodized interface have a relatively low concentration of positive fixed surface charge density, (1–3)×1011 cm−2, and fast surface state density per unit band gap of about 2×1011 cm−2 eV−1, measured at 77 K. The hysteresis in the capacitance-voltage characteristics of the MIS devices is negligible, indicating the near absence of slow-trapping effects which have been observed in anodic solution oxides. Photoconductors passivated with plasma oxide exhibit good responsivity and detectivity, indicating small surface recombination velocity and small interface trapping. A significant advantage of the plasma oxide is the excellent thermal stability of the interface. Devices such as MIS capacitors and photoconductors may be annealed in vacuum up to 95 °C for prolonged periods while retaining their properties.

Avalanche‐Induced Hot Electron Injection and Trapping in Gate Oxides on p‐Si

Hot electron trapping in gate oxides can lead to threshold drifts in short channel MOSFET's. Therefore, factors affecting the efficiency of hot electron trapping have been investigated by rf‐bias aging of MOS capacitors followed by flatband voltage measurements. It was found that avalanche‐injection electron current levels of >5 μA cm−2 produce excessive amounts of hot electron trapping; currents of <4 μA cm−2 were preferred for oxide characterization. A relatively small amount of hot electron trapping produced an enormous density of fast surface states. The observed flatband shifts would, therefore, contain significant contributions from surface states. The total flatband shift due to hot electron injection and trapping increased with higher p‐Si substrate doping levels and with increasing oxide thickness . Eectron beam irradiation (5–30 μC cm−2) followed by a 450°C, anneal did not significantly change the hot electron trapping behavior of the gate oxide. Possible implications of these results on the generic reliability of VLSI devices are discussed.

The interface between Hg 1− xCd xTe and its native oxide

The results of a study of the electrical properties of the interface between Hg 1− x Cd x Te with x = 0.21 and its native oxide at 77°K are presented. The native oxide is formed by anodic oxidation and results in an interface with reproducible properties. The surface charge, the surface mobility and the effective lifetime are obtained from galvanomagnetic measurements and are related to the semiconductor bulk parameters, the oxide thickness and the annealing conditions. The surface state charge and the metal-semiconductors work function difference are obtained from the shift of the flat band voltage of metal-oxide-semiconductor (MOS) capacitor characteristics. The interface between Hg 1− x Cd x Te and its native anodic oxide is characterized by a density of fast surface states of the order of 5 × 10 11cm −2 (eV −1) near the middle of the bandgap. The density of states increases towards the band edges to the order of 10 13cm −2 (eV −1). The measured flat band voltage is approximately −0.5 V for an oxide thickness of 500 Å and for an n-type semiconductor with an electron carrier concentration in the range 1–3 × 10 15 cm −3 at 77°K. The fixed oxide surface state charge is positive for both p-type and n-type semiconductors and is of the order of 6 × 10 11 charges per cm −2. The surface properties, the significance and the reproducibility of the results are evaluated.