Demultiplexer Circuit Research Articles

Optimising energy consumption in Nano‐cryptography: Quantum cellular automata‐based multiplexer/demultiplexer design

AbstractFuture global communications will depend heavily on nano‐communication networks, which use ultra‐low power nano‐circuits to transmit data efficiently at very high rates. An essential part of distributed communication networks is the circuit‐switched network, which distributes the input signal among several users. For designing nanoscale digital circuits, Quantum Cellular Automata technology (QCA) emerges as a formidable contender against the established complementary metal‐oxide‐semiconductor (CMOS) technology for low‐power devices. The authors endeavour to achieve an efficient design for multiplexer and demultiplexer switching circuits. The designed multiplexer and demultiplexer have 15 cells with an area of 0.02 μm2 and a latency of 0.5 clock cycles. The authors assess the energy dissipation and temperature impacts for both multiplexer and demultiplexer circuits. The novel design of switch circuits facilitates the sharing of a single communication link across multiple devices at the nano‐scale.

Fundamental 1:2 demultiplexer design in quantum-dot cellular automata nanotechnology

There are many issues with complementary metal oxide semiconductor (CMOS) technology in the ultra-nanoscale regime. A quantum-dot cellular automaton (QCA) is a promising innovation for crafting logic circuits in nanoscale dimensions. It provides lower power dissipation, better functionality, faster switching frequency, and better performance than that of the CMOS technology, which makes it a potential candidate for succeeding the CMOS technology. Demultiplexer is a needed operation to operate at the receiver side of the communication system, which converts the multiplexed data into original ones. Hence, a fundamental 1:2 demultiplexer is proposed using QCA technology. The proposed demultiplexer uses only 17 QCA cells and a single clock. The proposed 1:2 demultiplexer decreases the number of cells, hence occupying less layout area and a minimum clock as compared to the available works in the field. The proposed demultiplexer circuit improves the cell count by 19.05 %, the QCA clock by 50 % and the QCA cost by 64.25 % as compared to the best reported work in the literature. The energy dissipation of the suggested demultiplexer is examined using the QCA Designer-E and QCA Pro-tools. The proposed demultiplexer dissipates only 1.38 meV of average energy per cycle and is computed using the QCA Designer-E tool. The total energy dissipation for the proposed demultiplexer is improved by 22.85 % as compared to the best-reported work in the literature and is estimated using the QCA Pro-tool.

Broadband polarization/mode insensitive 3-dB optical coupler for silicon photonic switches.

In this work, we experimentally demonstrate a four-mode polarization/mode insensitive 3-dB coupler based on an adiabatic coupler. The proposed design works for the first two transverse electric (TE) modes and the first two transverse magnetic (TM) modes. Over an optical bandwidth of 70 nm (1500 nm to 1570 nm), the coupler exhibits at most 0.7 dB insertion loss with a maximum crosstalk of -15.7 dB and a power imbalance not worse than 0.9 dB. A multimode photonic switch matrix using this optical coupler is proposed simultaneously exploiting wavelength division multiplexing (WDM), polarization division multiplexing (PDM), and mode division multiplexing (MDM). Based on the coupler experimental measurements, the switching system loss is estimated to be 10.6 dB with crosstalk limited by the MDM (de)multiplexing circuit.

Power aware air quality sensing system with efficient data storage capability


 
 
 
 Introduction: This paper presents a portable device of Air QualityMonitoring System (AQMS) based on a sensor platform. The purpose of the study is to power awareness, warning indication, and minimal data storage capability.
 Materials and methods: AQMS is developed by embedded design methodology. The software part is based on the C programming language. AQMS device is made up of “transmitter” and “receiver” sections through the Zigbee wireless network. The objective is to collect concentrations of CO, NO2, CO2, humidity, and temperature to check air pollution for health awareness. A power-saving strategy is adopted in the "transmitter" of AQMS through a Demultiplexer circuit. To minimize the space complexity of storage and availability of long-term data, data encoding techniques are implemented.
 Results: By implementing switching activity on the sensors in AQMS, the active mode of sensing operations are controlled and a power saving of 18.41% is achieved. Extending the duration of transmission operation increases data storage in the “receiver” unit. Hence, two encoding techniques are developed where real-time data are encoded in binary form: 2-bit encoding and 3-bit encoding. According to the results, 2-bit encoding saves 50% of storage space and 3-bit encoding saves 25%, compared to not utilizing any encoding strategy, sacrificing data accuracy by less than 5%.
 Conclusion: AQMS design is created with the implementations of low power consumption and low storage. Additionally, an alarming condition is set in AQMS for indicating the level of pollutants in the air to determine the risk level of exposure which is dangerous for human health.
 
 
 

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Single‐Contact, Four‐Terminal Microelectromechanical Relay for Efficient Digital Logic

AbstractNano and microelectromechanical relays can be used in lieu of transistors to build digital integrated circuits that can operate with zero leakage current at high operating temperatures and radiation levels. Four‐terminal (4‐T) relays facilitate efficient logic circuits with greatly reduced device counts compared to three‐terminal (3‐T) relay implementations. Existing 4‐T relays, however, require two moving contacts to simultaneously land on two stationary electrodes, which can adversely impact reliability, or have complex out‐of‐plane fabrication methods that can reduce yield and increase cost while having poor scalability. In this work an in‐plane four‐terminal relay with a single moving contact is demonstrated for the first time, through successful fabrication and characterization of prototypes with a critical dimension of 1.5 µm. Body biasing is shown to reduce the pull‐in voltage of this 4‐T relay compared to a 3‐T relay with the same architecture and footprint. The potential of the 4‐T relay to build efficient logic circuits is demonstrated by fabricating and characterizing a 1‐to‐2 demultiplexer (DEMUX) circuit using only two devices, a saving of eight devices over a 3‐T relay implementation.

Broadband plasmonic half-subtractor and digital demultiplexer in pure parallel connections.

Nanophotonic arithmetic circuits requiring cascaded Boolean operations are difficult to implement due to loss and footprint issues. In this work, we experimentally demonstrate plasmonic half-subtractor and demultiplexer circuits based on transmission-lines. Empowered by the unique polarization selectivity in the surface plasmon modal behaviors, both circuits are realized without cascading. The operations of the half-subtractor and demultiplexer can be performed using a single laser beam with three predefined linear polarizations. All of our experiments are performed using a 56fs laser providing greater than 12.5THz optical bandwidth. The experimental results are found in excellent quantitative accordance with numerical calculations. The photonic integrated circuit framework proposed in this work could pave the future avenue towards the realization of highly compact, multi-functional, on-chip integrated photonic processors.

Implantation of polarization rotation based ternary 3:1 multiplexer and 1:3 demultiplexer using optical micro ring resonator

All optical ternary 3:1 multiplexer and 1:3 demultiplexer circuits are proposed and explained using polarization rotation switch (PRS) in micro ring resonator (MRR). Ternary logic (radix=3) states are defined by the logic-0 (Low), logic-1 (Intermediate) and logic-2 (High) with different polarization states. Polarization rotation based ternary 3:1 multiplexer and 1:3 demultiplexer have been accomplished by exploiting the concept of the ternary AND or ternary MIN gate. The performance of scheme are analyzed by Stokes parameter (S1,S2,S3) and Jones matrix (ellipticity and azimuth in angle) in INTERCONNECT simulation software.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Realization of High-End Multiplexers and Demultiplexers using CSWAP Quantum Gate

CMOS technology is expected to come to an end in performance and accuracy due to limitations of the shirking of the transistors. To overcome these limitations, researchers are working towards the development of quantum circuits that provide high-speed processing. In this work, high-end quantum multiplexer and demultiplexer circuits are proposed using a controlled SWAP (CSWAP) gate with low quantum cost. The proposed circuits are implemented using quantum gates and simulated to reduce complexity and improve performance. The software tool used for the design and simulation of the proposed structures is IBM Qiskit with python coding. It is observed from the simulation results that the proposed multiplexers are improved by more than 28% compared with the existing designs available so far in the literature.

Optimal design for 1:2n demultiplexer using QCA nanotechnology with energy dissipation analysis

AbstractQuantum‐dot cellular automata (QCA) is an emerging technology to design logic circuits at the nanoscale level. It has the potential to replace the complementary metal oxide semiconductor (CMOS) technology. In this paper, an optimal, single layered, single clocked 1:2 demultiplexer (DeMux) circuit is proposed using 19 QCA cells in QCA technology. Proposed 1:2 DeMux circuit is further utilized for designing of 1:4 DeMux and 1:8 DeMux circuits using 72 and 206 QCA cells respectively. DeMux is an important module at the receiver side in the communication system. The performance of the proposed DeMux circuits are checked and compared with the available similar designs using QCA Designer‐E. Proposed 1:2 DeMux decreases 79.17% layout cost and 50% clock latency as compared to the best reported work in the literature. Proposed 1:4 DeMux reduces 48.57% cells count and 40.63% total area while proposed 1:8 DeMux cuts 63.54% cells count and 64.54% total area as compared to best reported similar works in the literature. Energy dissipation pays an important role to design the energy efficient circuits at nanoscale level. Energy dissipations are estimated using QCA Designer‐E and QCA Pro tools. Proposed 1:2 DeMux saves 8.20% total energy dissipation as compared to the existing design.

Compact silicon-photonic mode-division (de)multiplexer using waveguide-wrapped microdisk resonators.

We experimentally demonstrate, to the best of our knowledge, the first microdisk-based silicon-photonic mode-division (de)multiplexer circuit, which is compatible with wavelength-division multiplexing for high aggregate bandwidth on-chip optical communications. This circuit uses waveguide-wrapped microdisk resonators, featuring low levels of intermodal crosstalk and insertion loss within an ultracompact footprint. In addition, the proposed device presents an increased free spectral range, allowing for 530 combined data channels. Furthermore, the microdisk structure naturally supports vertically oriented depletion-type pn junctions, which have been shown to reach subfemtojoule-per-bit modulation efficiencies. The high modulation efficiency, compactness, and wide free spectral range of waveguide-wrapped microdisk resonators present the potential for higher bandwidth and lower energy consumption in next-generation data processing and communication applications.

All-optical integrated 2-to-4 decoder and 1-to-4 demultiplexer circuit with enable using SOA based MZI

Abstract In this paper, we propose an all-optical integrated 2-to-4 decoder and a 1-to-4 demultiplexer circuit using SOA based MZI (Mach–Zehnder Interferometer) architecture. The proposed device has been applied an enable signal along with two data input signals at the same wavelength. Four output signals from 2-to-4 decoder and 1-to-4 demultiplexer have been attained at the same wavelength. The output timing diagrams of 2-to-4 decoder and 1-to-4 demultiplexer for different input data conditions with clear eye opening patterns confirms the operation of the proposed logic device at 10 Gb/s. Maximum value of extinction ratio, contrast ratio and minimum value of amplitude modulation achieved for the different output waveforms are 12, 9.5 and 0.1 dB respectively. Easy integration with active and passive devices and simple architecture makes this device suitable for all-optical processing.

Subchannel drop and add operation by using silicon photonic all-optical orthogonal frequency division multiplexing demultiplexers.

This study investigates the subchannel drop and add operation of a silicon photonic all-optical orthogonal frequency division multiplexing demultiplexer (O-OFDM-DEMUX) circuit. The proposed device consists of two O-OFDM-DEMUX circuits with four subchannels at a frequency spacing of 10 GHz and four 2×2 Mach-Zehnder interferometer (MZI)-type optical switches for drop and through operations, with another four 2×2 MZI-type optical switches for add and through operations. A subchannel on-off ratio of over 20 dB was achieved. In addition, a new subchannel was successfully added to the target subchannel, although the shape of the transmissivity spectrum was slightly degraded through the detuning of the spectrum.

Magnetic Demultiplexer Circuit with Four Channels

We present a magnetic demultiplexer that allows us to transfer a magnon from one guide to another without perturbation the other guides. The proposed devise is formed by introducing a resonant system between two infinite guides. The resonant system has the role of coupling the guides to allow the magnons to pass from one guide to another for a well-defined frequency. The filtered frequency depends on the lengths of the different elements that constitute the system. In the analytical calculations we demonstrate how to choose the geometrical parameters to get total transmission.

Versatile Visual Logic Operations Based on Plasmonic Switching in Label-Free Molybdenum Oxide Nanomaterials.

Despite some visual colorimetric chemical logic gates having been reported, a complete set of six basic logic gates have not been realized to date. Moreover, the application of the reported logic gates needs to be further extended. Herein, the label-free molybdenum oxide nanomaterials are presented for the construction of a new visual colorimetric molecular computing system. A complete set of six basic colorimetric logic gates (OR, AND, NOR, NAND, XOR, XNOR) and the INH logic gate are realized based on plasmonic switching in MoO3 nanomaterials. In addition, the rational integration of different logic gates into a 1:2 demultiplexer circuit is also testified.

Dual-Channel AND Logic Gate Based on Four-Wave Mixing in a Multimode Silicon Waveguide

We experimentally demonstrate on-chip dual-channel all-optical AND logic operations based on four-wave mixing (FWM) for on-off keying (OOK) signals in a multimode silicon waveguide. A two-mode (de)multiplexing circuit consisting of tapered directional coupler-based (de)multiplexers and a multimode waveguide is designed and fabricated for this application. Experimental results show open eye-diagrams and confirm the logic operations with moderate power penalties for both modes.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Analysis of silicon waveguide structure for realization of optical MUX/DEMUX circuit: An application of silicon photonics

Structure, operation and simulation of optical multiplexer and demultiplexer using silicon waveguide structure is discussed in this paper. Here silicon waveguide structure is realized by eighty three layers of waveguide in such way that it consists of 42 layer of silicon and 41 layer of air materials in an alternate manner. Here both reflection and absorption losses are considered to realize MUX/DEMUX. Simulation for reflectance is done using plane wave expansion method, where absorption loss is found zero for all wavelengths. Simulation results revealed that number of layers of waveguide, thickness of odd and even layers; structure period and length play an important role to design optical multiplexer and demultiplexer circuit. Present simulation result showed that waveguide having thickness of odd layer (silicon) 1180nm and even layer (air) 200nm, allows wavelength 850nm and reflects wavelength 1310nm and 1550nm. Similarly, structure having thickness, 180nm of odd layer (silicon) and 300nm of even layer allows wavelength 1310nm and reflects to both 850nm and 1550nm. And thickness of 80nm (odd) and 180nm (even) allows 1550nm and reflects both 850nm and 1310nm. Apart from this it is also seen that same waveguide structure having thickness of odd layers, 1nm and even layers, 999nm allows all wavelengths (850nm, 1310nm and 1550nm).

Design of ternary Multiplexer and De-multiplexer circuit with optical nonlinear material (OPNLM) based switch

Multiplexer and De-multiplexer operation play a very important role in all-optical computation, communication and control. Considerable number of multiplexing – de-multiplexing scheme in digital optical processing have already been reported. A design of all-optical ternary Multiplexer De-multiplexer circuit with optical nonlinear material (OPNLM) based switch is proposed and described in this paper. Different logic states have been represented by different polarization states of light. Logical simulation is also included here. This circuit will be useful in future all-optical multi-valued logic based computing and information processing system.