Demultiplexer Circuit Research Articles

Ultrahigh-speed heterojunction bipolar transistor multiplexer/demultiplexer ICs

High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively. >

11.6 Gbps 1:4 demultiplexer using double pulse doped quantum well GaAs/AlGaAs transistors

An ultrahigh speed 4 bit demultiplexer circuit has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3 μm gate length. First results show a data rate of 11.6 Gbit/s and a power consumption of 165 mW at 0.85 V supply voltage, including four 50 Ω buffers.

Multiplexing input options of VLSI circuits implemented in four-phase dynamic logic technology

Four-phase dynamic logic has been widely used to implement VLSI circuits. A technique which allows system designers to operate a custom-designed integrated circuit in different modes is to connect an input option pin to either a logic level 1 or a logic level 0 according to the specification by connecting it to V cc or ground respectively. This method allows the designer to configure the operation of the circuit in one of the two modes. In this paper it is shown that each pin can be used to offer four modes of operation instead of two by the use of a simple multiplexing circuit. The circuit was simulated and its operation verified using the industry-standard program SPICE. The additional area required to implement the demultiplexing circuit on the chip may be offset by the saving achieved by the use of one pin to input four variables instead of two pins. Removal of an input pin from the integrated package results in the saving of silicon area on the chip as it eliminates the contact pad area and the associated input gate protection circuitry.

5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.

Electronic Circuits for High Bit Rate Digital Fiber Optic Communication Systems

This paper describes electronic components for digital fiber optic transmitters and receivers with bit rates from several hundred Mbits/s up into the Gbits/s range. In particular, drivers and multiplexers suitable for direct laser modulation were developed for use in the transmitter units. A laser light output control circuit for independent stabilization of the minimum and peak to peak laser light output levels is described. A demultiplexer and clock regenerator circuit was developed for optical receivers. All high speed components were realized in thin film hybrid integrated technology using silicon bipolar transistors, Schottky diodes and step recovery diodes.