Delay-locked Loop Research Articles

A 2.5–5.0-GHz Clock Multiplier With 3.2–4.5-mUIrms Jitter and 0.98–1.06 mW/GHz in 65-nm CMOS

We present a two-stage cascaded clock multiplier with roughly constant energy consumption across 2.5-5.0GHz frequency range. The proposed clock multiplier consists of a reconfigurable delay-locked loop and edge combiner in the first stage while generating a 156.25-312.5MHz clock from 39.0625MHz reference clock frequency. An injection-locked clock multiplier with a frequency tracking loop in the second stage implements a 2.5-5.0 GHz output clock. The clock generation architecture is optimized for the clock multiplication ratio in the two stages and overall power consumption. Designed in TSMC 65nm CMOS process and characterized with post-layout simulations, the first-stage clock multiplier achieves an integrated jitter 1.396-0.607ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 156.25-312.5MHz frequency range at 1.15-2.82mW power consumption. The two-stage clock multiplier gives the total output jitter 1.5-0.9ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 2.5-5.0 GHz output frequency with 0.98-1.06mW/GHz power dissipation.

Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques

Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques

High-resolution LiDAR using random modulated continuous wave with a low code rate

Light detection and ranging (LiDAR) is essential to improving the reliability of autopilot technology. In this paper, we propose a new laser-ranging method for three-dimensional micro-electro-mechanical system LiDAR. First, a mathematical model is presented and the analytical solution for real-time calculation derived. Then, the mixed M-sequence and data code modulates the laser diode by pulse amplitude modulation. Finally, the resolution is enhanced by the matched filter and delay-locked loop technique, lowering the requirement of the code rate and analog-to-digital-converter sampling rate. Analytical and experimental results demonstrate that a distance precision of less than 2 cm and acquisition time within 8 ns (125 MHz) can be achieved, while the processing gain reaches 48 dB. In addition, this enhanced performance is maintained over long distances without periodic ambiguities, making it ideal for range imaging.

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL &lt; tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL &gt; tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz.

Signal Tracking Algorithm With Adaptive Multipath Mitigation and Experimental Results for LTE Positioning Receivers in Urban Environments

Positioning with cellular signals has been gaining attention in urban and indoor environments, where global navigation satellite system signals have limited availability due to interference, blockage, or multipath. However, accurate and reliable tracking of cellular signals under highly dynamic urban channel conditions remains a challenging task. This article presents a cellular long-term evolution (LTE) signal tracking algorithm implemented by an adaptive multipath estimating delay lock loop (AMEDLL) to achieve carrier phase synchronization and time-of-arrival (TOA) tracking under severe multipath propagation conditions. The analytical expression of the coherently integrated correlation result over multiple slots with the LTE cell-specific reference signal is derived. A multipath estimator along with a simple yet efficient multipath estimation monitoring approach is developed to estimate the parameters of all detected multipath signals. Several heuristic monitoring criteria based on historical multipath parameter estimations are established to enable adaptive adjustment of the estimated path number. Real LTE signals are collected in an urban environment for the signal tracking performance evaluation. This article presents two case studies with varying levels of multipath effects and signal power to illustrate the effectiveness of the developed signal tracking algorithm. Instead of a TOA truth reference, open-loop carrier phase estimations are used to analyze the TOA tracking error. Our analyses demonstrate that the AMEDLL-based tracking algorithm provides improved TOA estimation accuracy over the existing super-resolution-algorithm-based and delay-lock-loop-based tracking schemes.

Impact of neutron induced Single-Event Multiple Transients in ADDLL based frequency multiplier

This paper presents the impact of radiation-induced Single-Event Multiple Transients (SEMT) in All Digital Delay-Locked Loop (ADDLL) and its impact on the output of frequency multiplier. The performance of the frequency multiplier such as the phase noise and jitter etc. are degraded due propagation of the SEMT from the ADDLL. This paper: (1) shows the impact of SEMTs in the ADDLL in modern technologies, (2) shows how the frequency multiplier circuit performance can vary depending on the severity of SEMTs effects, and (3) demonstrates proposed edge-combined ADDLL based frequency multiplier performance benefits for more reliable operation.

Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing

In an IC used for safety-critical applications, the Fault and soft-error tolerance (or FET) is often desirable. In this work, we consider a graceful degradation scheme, as the second line of defense, for a FET delay-locked loop (DLL) we have recently developed. By doing so, a FET DLL will not operate blindly when its tolerance to faults or soft errors has been degraded. This is achieved by incorporating a novel low-cost excessive phase-error monitor. Any excessive phase error beyond a prelearned phase-error tolerance range will trigger an alarm of failure. This monitor can also be used to support an online test for deciding whether there is a faulty module in our TMR-based FET DLL at any given time. We have implemented the proposed scheme in a 90-nm CMOS process. The results show that the area of this excessive phase error monitor is as small as 60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times $ </tex-math></inline-formula> 60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,=$ </tex-math></inline-formula> 0.0036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , or only 4.12% of the entire FET DLL.

A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively.

High Resolution CMOS Frequency-to-digital Converter for a Fine Dust Sensor using a MEMS Resonator

A high resolution, low power CMOS oscillator and frequency-to-digital converter for a fine dust sensor using a MEMS resonator is proposed. The proposed frequency-to-digital converter is realized based on dual-loop hybrid delay-locked loop to distinguish fine frequency variations according to very small fine dust concentrations, and simultaneously applied binary and square search algorithms to obtain accurate digital codes indicating frequency changes. An oscillator and frequency-to-digital converter for a fine dust sensor is implemented using the 0.18-μm CMOS process. The core size of the fabricated MEMS oscillator and frequency-to-digital converter is 0.9 mm² and consumes about 16 mW of power at 1.8 V supply voltage. The proposed frequency-to-digital converter covers the input frequency range of 1.7 GHz to 2.3 GHz with 1 bit resolution of about 3 MHz.

A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS

We present a low-power and low jitter two-stage 2.46&#x2013;4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a <inline-formula> <tex-math notation="LaTeX">$64\times $ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">$128\times $ </tex-math></inline-formula> clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs_rms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving &#x2212;53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fs_rms at 4.92 GHz, &#x2212;28.2-dBc reference spur, and 3-mW power consumption.

Digital V2 Controller IC Using Delta Operator and Improved Average Predictive Control for DC–DC Converters With Fast Transient Response

Owing to its fast transient response, the V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> control technique for switching converters has wide potential application prospects. In this article, we present a digital V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller integrated circuit (IC) for dc–dc switching converters to improve the transient response. The controller IC consists of two compensators and some ancillary circuits, specifically a proportion-integral-differential (PID) compensator and a predictive control compensator, as well as an analog-to-digital converter (ADC) and a digital pulsewidth modulator (DPWM). The PID compensator is designed based on the delta operator instead of the conventional shift operator, which can improve the stability of the converter and reduce hardware costs. The predictive control compensator uses an improved average predictive control strategy to enhance the transient response. A 6-b delay-line window ADC with a differential bias circuit is proposed to improve the ADC linearity. An 11-b hybrid DPWM, which consists of a counter and a segmented delay line with a delay-locked loop (DLL), is proposed to relieve the conflict between the die area and DPWM linearity. A prototype of the digital V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller IC was fabricated using the 180-nm CMOS process, which was applied to a buck dc–dc switching converter to verify its performance. The experimental results show that an excellent transient response was achieved.

Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction

A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a na&#x00EF;ve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit&#x2019;s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL&#x2019;s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only na&#x00EF;ve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction.

A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications

ABSTRACT A fully integrated 2-transmitter–4-receiver (2TX–4RX) multiple-input multiple-output (MIMO) radar front-end in the 57–64-GHz band for short-range applications is presented in this paper. The proposed architecture with 8 elements within a one-dimensional virtual array enables theoretical angular resolution down to . The TX chains operate in time-division multiplexing (TDM) mode, and each delivers 12 dBm of saturated output power with output-referred 1-dB compression point (OP1dB) larger than 5 dBm over 7-GHz bandwidth. The millimeter-wave (mm-wave) part of the RX chains has a noise figure lower than 13 dB, and a conversion gain of 17 dB in the 60-GHz unlicensed band. The receiver chain shows a maximum conversion gain of 77 dB, while achieving an input-referred 1-dB compression point (IP1dB) greater than – 12.5 dBm, including baseband circuitry. The programmable baseband processing chain with 60-dB gain allows beat frequency selection in the frequency range from 100 kHz up to 1.3 MHz. Linear chirps are synthesized using a fractional-N phase-locked loop (PLL) with a fundamental voltage-controlled oscillator (VCO). The integrated system includes a programmable multiplying delay-locked loop (MDLL) which scales-up external high purity 40-MHz frequency reference to a referent 240-MHz clock used in the frequency-modulated continuous-wave (FMCW) synthesizer. The front-end is implemented in a 130-nm SiGe:C BiCMOS process. The chip occupies an area of 12 mm2 including pads and consumes 930 mW, combined from 1.2-V and 3.3-V supplies.

Charge Pump Using Gain-Boosting and Positive Feedback Techniques in 180-nm Digital CMOS Process

The charge pump (CP) circuit is an essential element in a delay-locked loop (DLL). This paper proposes a new CP using gain-boosting technique. Two possible solutions for gain-boosting circuit implementation are presented. One solution is based on common-source amplifier. In another solution, positive feedback method is employed at the output stage to increase the output resistance of the amplifier. Therefore, DC-gain of the amplifier is improved. In addition, nonlinear current mirror is employed in which the gain is dependent to the input current. To evaluate the performance of the proposed CPs, simulations are done in a 0.18 μm CMOS process with the supply voltage of 1.8 V. The simulation results indicate that the proposed CPs can obtain good current matching characteristics in the low power applications. The mismatch between up and down CP currents is less than 1%.

A mm-Wave Switched-Capacitor RFDAC

This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {{P_{\mathrm{ out}}}}&gt;21$ </tex-math></inline-formula> dBm, drain efficiency >36%, and system efficiency >22% while operating in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).

A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop

An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear approximation and z-domain PN model are utilized to simplify the analysis with excellent agreement between the time-domain simulation and z-domain approximation. The influences of the asymmetric waveform, flicker noise corner, frequency error and reference noise are also discussed and then ignored based on the reasonable approximation. Under a given process, reference clock frequency and supply voltage, the ideal FOM can be derived theoretically. Based on these insights, the predicted FOM can be the benchmark metric in the design of MDLL for the possible best jitter-power performance.

A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL

A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18 {\mu }\text{m}$ </tex-math></inline-formula> CMOS process and its active area is 0.185mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of −111.83dBc/Hz and −116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is −50.3dBc.

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

Tracking Digital FM OFDM Signals for the Determination of Navigation Observables

<h3>Abstract</h3> Methods are developed to acquire and track orthogonal frequency division multiplexing (OFDM) digital FM radio signals. These methods are being developed with the goal of using FM signals’ pseudorange and accumulated delta-range observables to navigate. Delay lock loop and phase lock loop discriminator outputs are computed by solving an optimal fitting problem in the frequency domain for each OFDM symbol. Single-differencing of the signals’ observables between a roving user receiver and a reference station receiver can remove transmitter clock drift effects. Wideband data collected in Roanoke, Virginia, and in Charlotte, North Carolina, have been processed offline and used to study these signals’ suitability for navigation. Single-differenced pseudorange measurement and bias errors relative to a base station can be on the order of 100 m, but single-differenced accumulated delta-range precision can be better than 0.1 m. A system that uses accumulated delta range may be able to yield 5-m level positioning accuracy if multipath effects can be compensated for. The present study represents an initial effort toward the goal of achieving this level of accuracy. Only pseudorange-based navigation is tested here, however, and its observed errors are on the order of 500 m.