Abstract
This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {{P_{\mathrm{ out}}}}>21$ </tex-math></inline-formula> dBm, drain efficiency >36%, and system efficiency >22% while operating in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).
Highlights
S INCE the introduction of “digital RF” [1], digital transmitters (TXs) have gained a lot of interest due to their amenability to CMOS technology scaling
The output of each local in-slice delay-locked loop (DLL) is fed to the corresponding RF digital-to-analog converter (RFDAC) bit-slice unit cell, which contains the logic mixer, the driver, and the edged combining (EC) output stage tripler to bring the frequency from f2 to f3 = 9 × fLO at the RFDAC output pad
Prototype of the fully integrated K a-Band SC-RFDAC was fabricated in a 22-nm FD-SOI process with 11 metal layers
Summary
S INCE the introduction of “digital RF” [1], digital transmitters (TXs) have gained a lot of interest due to their amenability to CMOS technology scaling. CMOS analog PAs are dominant at mmW frequencies, with many architectures proposed to obtain improved performance in key metrics of linearity, output power, and efficiency. Outphasing and Doherty architectures have proven reliable in improving back-off efficiency They require a complex passive output network to implement that may limit usable bandwidth. Due to the high frequency of operation, generating the LO to switch the output stage is challenging and consumes significant power, causing the degradation of ηSE ➁. This signal controls a parallel bank of switches/current sources that are summed/combined at the output before being fed to the antenna ➂.
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