Delay-insensitive Research Articles

MOR: Multi-objective routing for underwater acoustic wireless sensor networks

Underwater acoustic wireless sensor networks (UAWSN) are becoming more and more extensive, and different application scenarios have different service quality requirements. Routing protocols that can meet different traffic transmission requirements are vital to the application of UAWSN in different scenarios. Due to the harsh environment of the underwater acoustic channel, the routing protocol of the UAWSN should consider the characteristics of the underwater channels. In this paper, a multi-objective routing (MOR) scheme is proposed for UAWSN applications, and relay selection algorithms (RSA) are devised for delay-sensitive (DS) and delay-insensitive (DIS) scenarios to meet different quality-of-service (QoS). For DS applications, RSA selects the relays taking into account of the energy and delay affected mainly by MAC time, node congestion and hops of the nodes for connecting from potential candidate node to sink, while the RSA mainly takes energy consumption and reliability into consideration for DIS case to choose desired relay. The results demonstrated that the MOR outperforms VBF and QELAR in terms of delay and energy consumption for DS applications, while it is performs better in terms of delay, energy consumption, packet delivery rate and lifetime for DIS applications.

Emergence of universal global behavior from reversible local transitions in asynchronous systems

Reversible computing usually focuses on how to establish a valid equivalence between the global reversibility and local reversibility in computational systems. Hitherto the equivalence has been precisely developed in cellular automata, combinational circuits and quantum computers, but it implicitly assumes that the underlying systems are synchronously timed. Alternative systems include the delay-insensitive (DI) circuits and asynchronous cellular automata (ACAs), where the local operations of each component (cell) may be executed independently at random times. Despite the randomness associated with asynchronous timings, equivalence between the global and local reversibility can be simply achieved in both DI-circuits (Morita, 2001) and ACAs (Lee et al., 2003), provided that their local operations (transitions) are thoroughly serialized. The complete exclusion of concurrency in local behavior, however, will profoundly depress the parallel processing efficiency of DI-circuits as well as the intrinsic massive parallelism of ACAs. This paper aims at exploring what kind of complex global behavior may arise from the concurrent operations that are invertible at local level. To this end, we show that DI-circuits composed of reversible elements can actually exhibit universal input and output behavior, with the universality emerging from the concurrency in reversible local operations. Likewise, by further embedding all circuits into the cellular space, the emergence of universal global transitions from reversible local transitions can be exactly identified in an ACA which, due to the bijectivity of its local function, has significantly lower complexity as compared to other models.

Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.

SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC

This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based on the notion of section-carry is discussed. Three types of CLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed CLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications — here; this concept is applied to effect latency reduction in self-timed CLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a CLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.

An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally-Synchronous Systems

Contemporary digital systems must necessarily be based on the System-on-Chip (SoC) concept. Especially in relation to the aerospace industry, these systems must overcome some additional engineering challenges concerning reliability, safety and low power. An interesting style for aerospace SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used for Very Large Scale Integration - Deep-Sub-Micron (VLSI_DSM) design. Currently, the major drawback in the design of a GALS system is the asynchronous interface (asynchronous wrapper - AW) when being implemented in VLSI_DSM. There is a typical AW design style based on asynchronous controllers that provides communication between modules (called ports), but the port controllers are generally subjected to essential hazard, what decreases the reliability and safety of the full system. Concerning to this main drawback, this paper proposes an AW with robust port controller that shows to be free of essential hazard, besides allowing full autonomy for the locally synchronous modules, creating fault tolerant systems as much as possible. It follows the Delay Insensitive (DI) model interacting with the environment in the Generalized Fundamental Mode (GFM) without the need to insert any delay elements. Additional delay elements, although proposed by some previous work found in literature, are not desirable in aerospace applications. The proposed interface allows working on Ib/Ob mode, showing the DI model is more robust than the QDI model and, therefore, it does not need to meet isochronic fork requirements nor timing analysis. Once an interface presenting similar properties was not found in literature, the proposed architecture proved to have great potential of implementation in practical VLSI_DSM designs, including the aerospace ones, once it overcomes the main engineering challenges of this kind of industry.

Resilient and adaptive performance logic

As VLSI technology continues scaling, increasingly significant parametric variations and increasingly prevalent defects present unprecedented challenges to VLSI design at nanometer scale. Specifically, performance variability has hindered performance scaling, while soft errors become an emerging problem for logic computation at recent technology nodes. In this article, we leverage the existing Totally Self-Checking (TSC)/Strongly Fault-Secure (SFS) logic design techniques, and propose Resilient and Adaptive Performance (RAP) logic for maximum adaptive performance and soft error resilience in nanoscale computing. RAP logic clears all timing errors in the absence of external soft errors, albeit at a higher area/power cost compared with Razor logic. Our experimental results further show that dual-rail static (Domino) RAP logic outperforms alternative Delay-Insensitive (DI) code-based static (Domino) RAP logic with less area, higher performance, and lower power consumption for the large test cases, and achieves an average of 2.29(2.41)× performance boost, 2.12(1.91)× layout area, and 2.38(2.34)× power consumption compared with the traditional minimum area static logic based on the Nangate 45-nm open cell library.

A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits

Problem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or discrete time. Instead the circuits use handshaking between their components in order to perform the needed synchronization, communication and sequencing of operations. This difference gives asynchronous circuits’ inherent properties in the areas of lower power consumption, higher operating speed and robustness toward variations in supply voltage, temperature and fabrication process parameters, less emission of electromagnetic noise, better modularity, no clock distribution and clock skew problems. Low power consumption seems to be one of the most promising directions and the design reported in this study is one of these examples. Approach: In this study provide different solutions to these problems that the spectrum of existing asynchronous design technique support. It focuses on technique for fine grain two dimensional pipelining that yield ultra high speed at normal power supplies and very low energy at reduced power supplies. The new templates that provide significant performance improvements in quasi delay insensitivity. The key idea is to reduce the complexity of internal circuitry by intelligently reducing concurrency and using an additional wire for communication between pipeline stages. Results: In this study, Quasi Delay Insensitive RSPCHB template has been proposed to enhance the performance is faster with a maximum throughput of 970MHz than the previously designed system. Conclusion: The proposed model has been tested using HSPICE. The authors believe that the proposed design will provide a platform for designing high speed, low power digital circuits such as pipelined multiplier implemented in any application of digital signal processors.

Relativistic Causality and Clockless Circuits

Time plays a crucial role in the performance of computing systems. The accurate modelling of logical devices, and of their physical implementations, requires an appropriate representation of time and of all properties that depend on this notion. The need for a proper model, particularly acute in the design of clockless delay-insensitive (DI) circuits, leads one to reconsider the classical descriptions of time and of the resulting order and causal relations satisfied by logical operations. This questioning meets the criticisms of classical spacetime formulated by Einstein when founding relativity theory and is answered by relativistic conceptions of time and causality. Applying this approach to clockless circuits and considering the trace formalism, we rewrite Udding’s rules, which characterize communications between DI components. We exhibit their intrinsic relation with relativistic causality. For that purpose, we introduce relativistic generalizations of traces, called R-traces, which provide a pertinent description of communications and compositions of DI components.

Modeling and Verification of NCL Circuits Using PAT

NULL Conventional Logic (NCL) is a Delay-Insensitive (DI) clockless paradigm and is suitable for implementing asynchronous circuits. Efficient methods of analysis are required to specify and verify such DI systems. Based on Delay Insensitive sequential Process (DISP) specification, this paper demonstrates the application of formal methods by applying Process Analysis Toolkit (PAT) to model and verify the behavior of NCL circuits. A few useful constructs are successfully modeled and verified by using PAT. The flexibility and simplicity of the coding, simulation and verification shows that PAT is effective and applicable for NCL circuit design and verification.

혼합 지연 모델에 기반한 비동기 명령어 캐시 설계

최근에는 프로세서의 고성능화에 따라 명령어 캐시와 데이타 캐시를 분리하는 구조의 설계가 일반적이다. 본 논문에서는 혼합 지연모델을 갖는 비동기식 명령어 캐쉬구조를 제안하며, 데이타 패스에는 지연무관인 회로모델을 적용하고 메모리 에는 번들지연모델을 도입하였다. 요소기술로는 명령어 캐시는 CPU, 프로그램 메모리와 4-상 핸드쉐이크(hand-shake) 프로토콜로 데이터를 전달하고, 8-K바이트, 4상 연관의 맵핑 구조를 가지며 Pseudo-LRU 엔트리 교체알고리즘을 채택하였다. 성능분석을 위하여 제안된 명령어 캐시를 게이트레벨로 합성하고 32비트 임베디드 프로세서와 연동하는 플랫폼을 구축하였다. 구축한 플랫폼에서 MI벤치마크 프로그램을 테스트하여 99%의 캐시히트율과 레이턴시가 68% 감소하는 결과를 얻었다. Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

Automated energy calculation and estimation for delay-insensitive digital circuits

With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes a procedure to simulate a transistor-level design using a VHDL testbench, and then presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. Specifically, the VHDL testbench reads the transistor-level design's outputs and supplies the inputs accordingly, also allowing for automatic checking of functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. The energy estimation approach produces results three orders of magnitude faster than transistor-level simulation, and has been automated and works with standard industrial design tool suites, such as Mentor Graphics and Synopsys.Both methods are applied to the NULL Convention Logic (NCL) DI paradigm, and are first demonstrated using a simple NCL sequencer, and then tested on a number of different NCL 4-bit×4-bit unsigned multiplier architectures. Energy per operation is automatically calculated for both methods, using an exhaustive testbench to simulate all input combinations and to check for functional correctness. The results show that both methods produce the desired output for all circuits, and that the gate-level switching approach developed herein produces results more than 1000 times as fast as transistor-level simulation, that fall within the range obtained by two different industry-standard transistor-level simulators. Hence, the developed energy estimation method is extremely useful for quickly determining how architecture changes affect energy usage.

Differential Value Encoding for Delay Insensitive Handshake Protocol

Since the inception of Globally Asynchronous Locally Synchronous (GALS) VLSI design, GALS has been considered a promising design technique for multi-clock-domain System-on-Chip (SoC). Among the handshake protocols available for SoC design, delay insensitive (DI) handshake protocol is becoming a core technology, since it facilitates robust data transfer regardless of wire delay variation. In this paper, a new data encoding scheme Differential Value Encoding (DVE) is proposed for two-phase 1-of-N DI handshake protocol. Compared with the conventional data encoding method, the proposed scheme effectively reduces the crosstalk effect on wires sending sequentially increasing data patterns, resulting in reduction of the data transfer time. Simulation results with SPEC CPU 2000 benchmarks and sequentially increasing data pattern reveal that the DVE scheme can reduce the crosstalk effect by tens of percentage and significantly decrease the data transfer time.

Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism

Conventional delay-insensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-μm CMOS technology. Simulation results with wire lengths of 4mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5MHz or more and the 1-of-4 encoding with data rate of 18MHz or more.

Universal delay-insensitive systems with buffering lines

A delay-insensitive (DI) circuit is a type of asynchronous circuit that is robust to arbitrary delays in circuit elements or interconnection lines. This paper presents a new class of DI circuits of which interconnection lines have buffers that may contain multiple signals. We propose a set of three primitive circuit elements each of which has at most four lines for input or output. We prove that this set can be used to construct all valid DI circuits with buffering lines, i.e., that it is universal. Two more sets of three primitives with connectivity four are also presented, and their universality is shown. The limited number of primitives required in each universal set and the low connectivity of the primitives, as compared to previously proposed DI circuits, may facilitate efficient implementation of DI circuits in nanocomputer architectures based on asynchronous cellular automata.

Universal delay-insensitive circuits with bidirectional and buffering lines

Delay-insensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DI-circuits and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra and Fussell presented an alternative universal set of primitive modules and claimed that there is no universal set of primitives satisfying Keller's conditions in which the largest number of input and output lines of each primitive module is less than five. We present new types of primitive modules, each having at most three input and output-lines and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input and output-lines of modules to be bidirectional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of Dl-circuits is especially useful for implementations on cellular automata - an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure.

Delay insensitive RSFQ circuits with zero static power dissipation

Total power dissipation in RSFQ circuits consists of two parts, dynamic and static. Dynamic power is dissipated in Josephson junctions performing useful logical and data transmission operations. This dissipation is fundamental and proportional to the data rate (at 4 K, of the order of 10/sup -18/ Joule per bit). Static power is dissipated in resistors used by RSFQ circuits to distribute dc bias current between Josephson junctions. This part of dissipation is not intrinsic to RSFQ circuits and in principle can be eliminated. The goal of this work is to show that Delay Insensitive (DI) RSFQ primitives can be modified so that resistors are no longer required in the dc power supply distribution network, so that the on-chip static power dissipation is absent. In this report we present the schematics for such primitives, define the class of circuits that allow resistor-free current distribution network, and formulate the requirements to the design of this network.

Self-timed parallel adders based on DI RSFQ primitives

We present two versions of self-timed pipelined parallel carry-look-ahead adders. The adders are designed based on delay-insensitive (DI) rapid single-flux-quantum (RSFQ) primitives. Basic binary gates employ dual-rail encoded data, which include timing information in themselves. One version uses wave pipelining and the other delay-insensitive pipelining with a request-acknowledge data transfer protocol. We show simulation results of 4 to 32-bit adders and their sensitivity to delay variations. Two design schemes are compared in terms of area, speed, robustness, interface and design process for large systems.

Asynchronous comparison-based decoders for delay-insensitive codes

A comparison-based decoder detects the arrival of a code word by comparing the received checkbits with the checkbits computed using the received data. Implementation issues underlying comparison-based decoders for systematic delay-insensitive (DI) or unordered codes is the subject of this paper. We show that if the decoder is to be implemented using asynchronous logic, i.e., if the gate and wire delays are arbitrary (unbounded but finite), then it is impossible to design a comparison-based decoder for any code that is more efficient than a dual-rail code. In other words, the encoded word must contain at least twice as many bits as the data. In addition, the codes should satisfy two other properties, called the initial condition and the all-zero lower triangle (AZLT) property, for the realization of a delay-insensitive comparison-based decoder. The paper shows that comparison-based decoders for codes that have the requisite level of redundancy and that satisfy the two properties can be implemented using asynchronous logic.

On the realizability and synthesis of delay-insensitive behaviors

This paper presents six properties, each of which, if satisfied by all the basic circuit elements used in synthesis, will also be satisfied by any delay-insensitive (DI) behavior realized by those circuit elements. Six relevant theorems are proved. The DI behaviors of classical circuit elements (e.g., AND, OR, inverter, merge, etc.) are then examined. It is found that they all satisfy the so called unique successor set (USS) property. As a result, it is proved that any DI behavior realized by a network of classical circuit elements necessarily exhibits the USS property. Some new circuit elements are needed to realize arbitrary DI behaviors (e.g., those that do not exhibit the USS property). A set of circuit elements is proposed. It is shown that these circuit elements are sufficient to implement any determinate finite state DI system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design and characterization of a standard cell set for delay insensitive VLSI design

A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investigate the correspondence between theoretical formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We illustrate the new features involved in the electrical design and characterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cells have been fabricated. >