Universal delay-insensitive circuits with bidirectional and buffering lines

Abstract

Delay-insensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DI-circuits and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra and Fussell presented an alternative universal set of primitive modules and claimed that there is no universal set of primitives satisfying Keller's conditions in which the largest number of input and output lines of each primitive module is less than five. We present new types of primitive modules, each having at most three input and output-lines and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input and output-lines of modules to be bidirectional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of Dl-circuits is especially useful for implementations on cellular automata - an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure.