An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally-Synchronous Systems

Duarte Lopes Oliveira,Lester Abreu Faria,Sandro Shoiti Sato,Eduardo Lussari

doi:10.5028/jatm.v5i1.191

Abstract

Contemporary digital systems must necessarily be based on the System-on-Chip (SoC) concept. Especially in relation to the aerospace industry, these systems must overcome some additional engineering challenges concerning reliability, safety and low power. An interesting style for aerospace SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used for Very Large Scale Integration - Deep-Sub-Micron (VLSI_DSM) design. Currently, the major drawback in the design of a GALS system is the asynchronous interface (asynchronous wrapper - AW) when being implemented in VLSI_DSM. There is a typical AW design style based on asynchronous controllers that provides communication between modules (called ports), but the port controllers are generally subjected to essential hazard, what decreases the reliability and safety of the full system. Concerning to this main drawback, this paper proposes an AW with robust port controller that shows to be free of essential hazard, besides allowing full autonomy for the locally synchronous modules, creating fault tolerant systems as much as possible. It follows the Delay Insensitive (DI) model interacting with the environment in the Generalized Fundamental Mode (GFM) without the need to insert any delay elements. Additional delay elements, although proposed by some previous work found in literature, are not desirable in aerospace applications. The proposed interface allows working on Ib/Ob mode, showing the DI model is more robust than the QDI model and, therefore, it does not need to meet isochronic fork requirements nor timing analysis. Once an interface presenting similar properties was not found in literature, the proposed architecture proved to have great potential of implementation in practical VLSI_DSM designs, including the aerospace ones, once it overcomes the main engineering challenges of this kind of industry.

Highlights

Contemporary digital systems are usually implemented on Very Large Scale Integration (VLSI) and must necessarily be based on the “System-on-Chip” (SoC) concept
This paper proposes robust port controllers for asynchronous interfaces used in GALS style
In relation to aerospace applications, in which reliability and safety are major constraints, these drawbacks are prohibitive. Concerning this situation, a new architecture to asynchronous wrapper (AW) was proposed in order to overcome the previously discussed problems, showing to be a good option for those designers who need to implement GALS in VLSI_DSM, including for aerospace applications, once it improves the reliability of the system, eliminating essential hazards

Summary

Introduction

Contemporary digital systems are usually implemented on Very Large Scale Integration (VLSI) and must necessarily be based on the “System-on-Chip” (SoC) concept. SoC circuits are composed of functional modules, which can be the intellectual property cores (IP-cores) from many different vendors. These IP-cores are pre-designed, verified, tested and optimized for high-performance, providing both cost and development time reduction. Once SoC circuits are implemented in deepsub-micron (DSM) technologies (VLSI_DSM) (for example, 70 nm, 500M transistors for chip and f=2,5 GHz), delays caused by wires prove to be big when compared to the gate timing, and the difference between minimal and maximum delays in the gates is significant (Jain et al, 2001; Martin et al, 2006). When SoC circuits are implemented using only a global clock signal, they are subjected to speed and power penalties (clock skew, distribution networks etc.), making timing analysis very complex (Friedman, 2001). The harsh environment found in aerospace applications, with high temperature variations, can make this time analysis even more difficult

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Discussion

Conclusion