Delay Circuit Research Articles

Improved Mathematical Models of Parkinson's Disease with Hopf Bifurcation and Huntington's Disease with Chaos.

Using delay differential equations to study mathematical models of Parkinson's disease and Huntington's disease is important to show how important it is for synchronization between basal ganglia loops to work together. We used the delay circuit RLC (resistor, inductor, capacitor) model to show how the direct pathway and the indirect pathway in the basal ganglia excite and inhibit the motor cortex, respectively. A term has been added to the mathematical model without time delay in the case of the hyperdirect pathway. It is proposed to add a non-linear term to adjust the synchronization. We studied Hopf bifurcation conditions for the proposed models. The desynchronization of response times between the direct pathway and the indirect pathway leads to different symptoms of Parkinson's disease. Tremor appears when the response time in the indirect pathway increases at rest. The simulation confirmed that tremor occurs and the motor cortex is in an inhibited state. The direct pathway can increase the time delay in the dopaminergic pathway, which significantly increases the activity of the motor cortex. The hyperdirect pathway regulates the activity of the motor cortex. The simulation showed bradykinesia occurs when we switch from one movement to another that is less exciting for the motor cortex. A decrease of GABA in the striatum or delayed excitation of the substantia nigra from the subthalamus may be a major cause of Parkinson's disease. An increase in the response time delay in one of the pathways results in the chaotic movement characteristic of Huntington's disease.

Compact Broadband Negative Group Delay Circuit with Flatness and Bandwidth Enhancement

Compact Broadband Negative Group Delay Circuit with Flatness and Bandwidth Enhancement

Advancements in Dual-Function UV-Visible Light Detection

Abstract This research introduces a photodetector capable of differentiating between ultraviolet (UV) and visible light, employing the unique properties of zinc oxide (ZnO) and α-silicon (α-Si). The core of this innovative device is a pixel unit circuit, designed with three integral components: a delay circuit for precise timing, a photosensitive element composed of an α-Si thin film resistor and a ZnO thin film transistor (ZnO TFT) for respective light spectrum detection, and a source follower for effective signal transmission. Through simulations conducted in Cadence Virtuoso, the device’s responsiveness to varying intensities of UV and visible light was assessed. Adjustments to the α-Si resistance and ZnO TFT threshold voltage simulated realistic light conditions, demonstrating the device’s capability to generate distinct voltage changes in response to different light spectrums. These results underline the potential of the design for larger-scale implementations and highlight its adaptability and precision in detecting diverse light intensities. This research provides the basis for the development of simultaneous UV-visible detection and scalable light detection systems. In addition, taking advantage of the properties of ZnO TFT, which can also be used in the future in curved transparent environments.

Multi‐band pass negative group delay circuit with low insertion loss

AbstractA novel multi‐band pass negative group delay circuit has been designed and proposed. The circuit consists of three types of components: capacitance, inductance, and resistance. An n‐order bandpass negative group delay circuit was analyzed and presented, and taking a three‐frequency bandpass negative group delay circuit as an example, the influence of different component values on the circuit group delay and insertion loss was analyzed. The actual test results of this circuit are consistent with the simulation results, and it can achieve the function of a multi‐bandpass circuit. In actual testing, the circuit frequencies with negative group delay are 49, 82, and 102 MHz, with corresponding group delay values of −2.177, −2.058, and −1.903 ns and corresponding insertion loss values of −5.810, −5.835, and −5.866 dB.

Balanced bandpass filter with common-mode reflectionless and linear-phase characteristics based on negative group delay circuit

In this paper, a balanced bandpass filter (BPF) with common-mode reflectionless and linear-phase characteristics is proposed, which consists of a balanced 3-order bandpass filtering network and two common-mode absorptive networks to obtain the common-mode reflectionless and suppression performance. The negative group delay circuits are loaded on the proposed balanced BPF to realize the full-passband linear-phase filtering performance. The flatter the group delay of the BPF (the fluctuation of the group delay within the passband tends to 0), the better the phase-frequency linearity, which will realize the undistortion transmission of the communication systems. For demonstration, a balanced linear-phase BPF prototype operating at 1.5 GHz is designed, simulated, and manufactured. The results demonstrate that the group delay fluctuation is reduced from 1.20 ns to 0.11 ns by 90.8 %, the differential-mode insertion loss is 1.04 dB, the minimum common-mode suppression is 59.3 dB within the passband and the common-mode reflectionless band is 1.22–1.91 GHz. The developed topology requires high precision in the processing, and the proposed balanced BPF can be applied to digital microwave communication systems to improve the transmission quality and reduce the bit error rate.

Balanced Linear-Phase Bandpass Filter Equalized with Negative Group Delay Circuit

Balanced Linear-Phase Bandpass Filter Equalized with Negative Group Delay Circuit

Positive‐to‐negative tunable delay circuit designed with NGD RC network

SummaryDespite the performed progressive research work, the interpretation of the negative group delay (NGD) function remains not familiar to non‐specialist design and fabrication circuit engineers. The functionality misunderstanding limits the NGD circuit applications compared to other classical electronic functions. The present paper deals with the design of a tunable circuit by operating with positive and negative delay behaviors. The topology of the tunable circuit by using a low‐pass (LP) type NGD circuit is described. The design formulas for calculating the circuit resistor and capacitor parameters from the desired delay are expressed. The design feasibility of the tunable circuit composed of LP‐NGD cell and RC‐circuit is validated with a proof‐of‐concept (PoC) implemented on a test board. Two different signals with pulse and arbitrary waveforms having tens‐milliseconds duration were considered during the validation tests. As expected by tuning a varistor from 0.4 kΩ to 1 kΩ, the negative delay behavior varying from about −0.4 ms was verified thanks to the time‐advanced effect due to the LP‐NGD property. Then, the output signal delay was observed to become positive when the varistor was tuned from 1 kΩ to 3 kΩ.

A MoClo-Compatible Toolbox of ECF Sigma Factor-Based Regulatory Switches for Proteobacterial Chassis.

The construction of complex synthetic gene circuits with predetermined and reliable output depends on orthogonal regulatory parts that do not inadvertently interfere with the host machinery or with other circuit components. Previously, extracytoplasmic function sigma factors (ECFs), a diverse group of alternative sigma factors with distinct promoter specificities, were shown to have great potential as context-independent regulators, but so far, they have only been used in a few model species. Here, we show that the alphaproteobacterium Sinorhizobium meliloti, which has been proposed as a plant-associated bacterial chassis for synthetic biology, has a similar phylogenetic ECF acceptance range as the gammaproteobacterium Escherichia coli. A common set of orthogonal ECF-based regulators that can be used in both bacterial hosts was identified and used to create 2-step delay circuits. The genetic circuits were implemented in single copy in E. coli by chromosomal integration using an established method that utilizes bacteriophage integrases. In S. meliloti, we demonstrated the usability of single-copy pABC plasmids as equivalent carriers of the synthetic circuits. The circuits were either implemented on a single pABC or modularly distributed on 3 such plasmids. In addition, we provide a toolbox containing pABC plasmids compatible with the Golden Gate (MoClo) cloning standard and a library of basic parts that enable the construction of ECF-based circuits in S. meliloti and in E. coli. This work contributes to building a context-independent and species-overarching ECF-based toolbox for synthetic biology applications.

Systematic design of negative group delay circuits

In this brief, we introduce and verify some general opamp based structures to obtain negative group delay circuits. First order and second order negative group delay circuits are verified and all are noninverting circuits. As both the transfer functions and the group delay are simultaneously considered important derivations related to the actual bandwidth of operation are derived. LTSpice circuit simulations and experimental results using Gaussian input signals are provided to verify the theory.

Single CFOA-based active Negative Group Delay circuits for signal anticipation

The group delay of a signal prior to data monitoring is a crucial consideration in today’s real-time applications, especially for those that involve long sensor arrays or high-order filters. In this article, nine new second-order Negative Group Delay (NGD) circuits based on Current Feedback Operation Amplifier (CFOA) are proposed, and their transfer functions are demonstrated. These circuits have a wide range of applications, from audio to mechanical signals and sensor signal anticipation. An example design procedure is provided for one of the introduced circuits. A time-domain analysis is performed using both a single-tone sinusoidal and a band-limited audio recording in the frequency range of 1 Hz to 500 Hz. The article assesses the change in the signal using Root Mean Square Error (RMSE) and cross-correlation. Furthermore, the relationship between the NGD value and the operation range of the circuit is investigated and verified experimentally. The results show that an NGD value of approximately 100μs can be achieved with an amplitude error of 0.86% for a single-tone input and 1.54% for an audio recording, and an operation range of about 650 Hz.

On the fractional domain analysis of negative group delay circuits

SummaryIn this work, the analysis of negative group delay circuits in fractional domain has been conducted. The low pass and the high pass negative group delay circuits constructed based on passive network have been chosen as our candidate circuits. For performing the analysis in fractional domain, the novel Caputo–Fabrizio derivative‐based fractional impedance have been introduced to both circuits. The crucial parameters, the necessary conditions, and the existence conditions of both candidate negative group delay circuits have been formulated. The simulations have been conducted based on the formulated results where the comparisons with the conventional prototypes have been made. The verifications by the proof‐of‐concept circuits have also been performed. In addition, the effects of variation in the order of fractional impedances have been investigated. In summary, it has been found that considering these negative group delay circuits in the fractional domain, which effectively taking unavoidable nonidealities that cannot be modeled in conventional domain into account, significantly alters their characteristics especially the low pass circuit. However they can retain their low pass and high pass negative group delay functions.

Design of a quint-band passive NGDC by using Taguchi’s optimization method

This article presents a quint-band passive negative group delay circuit (Q-NGDC) by using Taguchi’s optimization method for the first time. This Q-NGDC mainly consists of a semi-circle and a multi-stub resonator, and it is evolved from a simple NGDC (Type I) to a well-designed one (Type VI) through three optimization stages. It is found that, with the application of Taguchi’s method (TM) in conjunction with full-wave simulations, the efficiency of the designed passive multi-band NGDC has been improved significantly. The proposed Q-NGDC was fabricated and tested, and the experimental results show that the five operation bands have been achieved at the center frequencies of 1.76, 2.80, 3.84, 4.42, and 5.28 GHz, with the corresponding group delay values of −1.85, −2.15, −1.45, −1.6, and −1.1 ns. The measured transmission coefficients are −4.4, −7.8, −9.7, −9.3, and − 8.9 dB. Furthermore, the proposed NGDC shows the best figure of merit (FOM) at each resonant frequency with a relatively small size. The proposed NGDC can be potentially applied to WCDMA, 5G communication, Zigbee (IEEE802.15.4), and Wi-Fi (IEEE802.11n) systems.

All-Pass NGD FIR Original Study for Sensor Failure Detection Application

This paper deals with original design, implementation, test, and potential application of finite impulse response (FIR) with uncommon all-pass negative group delay (AP-NGD) circuit. The counterintuitive AP-NGD numerical circuit theory is established. Design method of first order AP-NGD circuit is introduced with respect to the specified time-advance. The first order difference equation was synthesized, designed, and implemented in STM32 Microcontroller Unit, and experimented to validate the AP-NGD characteristics. The AP-NGD FIR prototype was tested in the time-domain with Gaussian and arbitrary waveform sensored signals. Calculated and experimented results in very good agreement with the most significant time-advance -10 s ever experimented before are obtained. The potential industrial application of the NGD predictor for sensor fault diagnosis in real-time is described.

Compact and Wideband Flat Negative Group Delay Circuit Investigation

This paper introduces a dual transmission structure with bandpass (BP) negative group delay (NGD) wideband flat behavior. The flat BP-NGD topology is analytically modelled from equivalent circuit composed of transmission line (TL) and stepped-impedance resonator connected by two resistors. As proof of concept (POC), by tuning TL characteristic impedances, the influences of circuit physical variables on NGD flatness are illustrated by parametric study. The flat BP-NGD POC circuit with a size of 48.2 mm×90.8 mm (0.2λg 0.38λg) is designed, fabricated, and measured. A very good agreement is confirmed by simulation and experimentation results of 680 MHz over 290 MHz (42.6%) NGD bandwidth (BW) around 0.7 GHz NGD center frequency. Also, the flat BP-NGD BW reaches 223 MHz (31.8%) over 569 MHz to 792 MHz with ±0.05 ns group-delay fluctuation with insertion and reflection losses better than 14 dB.

Group delay compensation based on negative group velocity effect of spoof surface plasmon polaritons

Negative group velocity (NGV) exists only in the anomalous dispersion band with resonance absorption. In this paper, it is verified that spoof surface plasmon polaritons (SSPPs) with spiral-shaped periodic units have the NGV characteristics near cutoff frequency. The negative group delay of this NGV SSPP can be used to achieve the compression of the pulse signal, and also to compensate the positive group delay with high efficiency. Of course, this group delay compensation scheme based on NGV may introduce an absorption loss, which is the characteristic of all passive negative group delay circuits.

Stabilizing the Boost PFC Converter with a Time Delay Feedback Controller

The One-Cycle Controlled Boost Power Factor Correction converter has one voltage control loop, which may exhibit instability when the load is light. The instability results in a low Power Factor. To ensure that the Power Factor is high, a time delay circuit was adopted in this paper to control the instability of the converter. The architecture of the time delay circuit is described, and its transfer function is derived. The double averaging method was applied to the converter to determine the parameters in the control method. Experimental results verified the time delay control method in the converter. The power factor increased from 0.82 to 0.99 after activating the delay control circuit.

Design theory of compact power divider with reconfigurable power division and negative group delay characteristics

This article presents the combined analysis of reconfigurable power division and negative group delay (NGD) in a power divider. A novel composite transmission line based reconfigurable power divider with high power division ratio, variable negative group delay, and lower characteristic impedance is presented in this work. The impedance transformation in composite transmission lines control both negative group delay and power division. This power divider possesses a wide range of power division ratios from 1 to 39, adequate isolation, impedance matching, and NGD of -3.4 ns to -4.7 ns in the reconfigurable transmission path. The negative group delay is achieved without using any additional group delay circuits. Theoretical equations corresponding to the low characteristic impedance of the transmission line sections and that of isolation elements are derived. The measurement results justify the attainment of high tuning of the power division ratio and negative group delay. Isolation and return loss are higher than − 15 dB at the centre frequency of 1.5 GHz. The significant contributions of this design can be listed as the wide reconfigurable power division along with negative group delay and reduced size.

A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology

This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$</tex-math> </inline-formula> -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/ fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up-and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> to 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> in a 7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.

Design and Analysis of a Multi−Carrier Orthogonal Double Bit Rate Differential Chaotic Shift Keying Communication System

A new multi−carrier orthogonal double bit rate differential chaotic shift keying (MC−ODBR−DCSK) communication system is presented in this paper. With two composite signals generated by an orthogonal chaotic signal generator as reference signals, 2M bits of information data are transmitted on M−channel subcarriers, improving transmission speed and energy efficiency. In addition, the receiver does not require a radio frequency (RF) delay circuit to demodulate the received data, which makes the system easier to implement. This paper analyzes Data−energy−to−Bit−energy Ratio (DBR) of the system. The bit error rate performance of the system is simulated to verify the impact of parameters such as chaotic maps, semi-spread spectrum factor, and sub-carrier number. At the same time, the bit error rate performance of the MC−ODBR−DCSK system is compared with traditional DCSK systems in Rician fading and additive Gaussian white noise (AWGN) channels.

OTA-C signal delay compensation circuit for transimpedance-mode audio signal processing systems

This paper proposes an operational transconductance amplifier-capacitor-based (OTA-C) negative group delay (NGD) circuit for transimpedance-mode systems. The application areas extend from audio to sensor signal anticipation. Post-layout simulated NGD value of about 200 μs to 100 ns is observed to be achievable with three different capacitor values without any resistive passive components. The operation range varies from 700 Hz to 700 kHz. The NGD and the operation range are shown to be flexible without gain dependency. An example design is built for a specific NGD value of 15 μs and time-domain analysis is done with both a single-tone sinusoidal and a band-limited audio record in the range of 1 Hz–7 kHz. The calculated Root Mean Square Error for audio input to the system is only 4.70%.