Delay Circuit Research Articles

CSRR DGS-Based Bandpass Negative Group Delay Circuit Design

The unfamiliar negative group delay (NGD) circuit is the less familiar function for most of RF and microwave design engineers. Among the existing types, the bandpass (BP) NGD type circuits are the most convenient for the wireless communication microwave technology. Therefore, it is particularly important to explore different microwave circuit topologies operating as BP-NGD function. An innovative design of BP-NGD topology constituted by defected ground structure (DGS) with complementary split ring resonator (CSRR) is developed in the present paper. The DGS-based BP-NGD structure design method is introduced in function of the CSRR geometrical elements followed by S-parameter parametric analyses. As proof-of concept (POC), the design method of the proposed BP-NGD passive fully distributed circuit is described. The effectiveness of the BP-NGD structure and the test feasibility are investigated by implementing two different prototypes represented by single- and double-wing DGS passive circuits. It is observed that significant BP-NGD function performances were validated by well-correlated simulations and measurements showing -1.9 ns NGD value around the center frequency, 2.46 GHz over 31 MHz NGD bandwidth. In addition, the tested BP-NGD prototypes present insertion loss better than 4 dB and reflection loss better than 16.7 dB. Because of its potential integration, the investigated BP-NGD circuit is potentially useful for the communication system performance improvement for example via delay effect reduction in the RF and microwave devices.

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application

In this article, a 1.25-V 8-Gb, 16-Gb/s/pin GDDR6-based accelerator-in-memory (AiM) is presented. A dedicated command (CMD) set for deep learning (DL) is introduced to minimize latency when switching operation modes, and a bank-wide mantissa shift (BWMS) scheme is adopted to minimize calculation delay time, current consumption, and circuit area during multiply-accumulate (MAC) operation. By storing the lookup table (LUT) in the reserved word line in the dynamic random access memory (DRAM) bank cell, it is possible to support various activation functions (AFs), such as Gaussian error linear unit (GELU), sigmoid, and Tanh as well as rectified linear unit (ReLU) and Leaky ReLU. Performance evaluation was conducted by measuring the fabricated chip in ATE and a self-manufactured field-programmable gate array (FPGA)-based system. In the ATE-level evaluation, it operates at 16 Gbps up to a voltage as low as 1.10 V. When evaluated by GEMV and MNIST in the FPGA-based system, it was confirmed that the performance gains of 7.5–10.5 times were possible compared to the HBM2-based or GDDR6-based systems.

Differential Negative Group Delay Circuit Topology with Reverse Nested Double U-shaped Defected Ground Structure

Differential Negative Group Delay Circuit Topology with Reverse Nested Double U-shaped Defected Ground Structure

Research and Simulation of Negative Group Delay and Superluminal Propagation

Abstract In recent years, negative group delay circuits have attracted much attention due to their propagation characteristics and wide application prospects. In the history of human exploration, the exploration of the speed of light has never stopped. The theory of relativity points out that the speed of light in vacuum is the limit speed of signal propagation. However, it is found through research that phase velocity and group velocity appear faster than the speed of light, which does not violate the causal relationship. This paper first introduces the related concepts of negative group delay and superluminal phenomenon, the second focuses on the principle of negative group delay and superluminal phenomenon in-depth analysis and research, finally using the principle of Multisim software, the bandwidth of two different job, different structure of circuit design, the virtual simulation experiment to negative group delay phenomenon and measurement data. It is of great significance to explore the field of faster-than-light and negative group delay in today's rapidly developing information age, and it can try to meet the high requirements for signal transmission. In the future, the interdisciplinary research direction of this research topic also has great development space.

A Compact Passive Quad‐Band Negative Group Delay Circuit With Stepped Impedance Resonator and Defected Microstrip Structure

AbstractBased on two‐stage stepped impedance resonator (SIR) and defected microstrip structure (DMS) with an E‐shaped slot, a novel compact passive quad‐band negative group delay circuit (NGDC) is proposed whose resonation frequencies and group delay performance are mainly determined by the SIR and the DMS. In order to help reveal the working mechanism of the quad‐band NGDC, an equivalent circuit of the NGDC is developed. It is composed of the transmission lines and serial‐parallel LC networks, and its S‐parameters are derived by using the theory of transmission matrix. The theoretical and simulated results for the transmission characteristics of the NGDC agree well with each other. To validate the design concept, a prototype of the proposed quad‐band NGDC was fabricated and measured. The measured results show that at the frequencies of 2.64, 7.88, 13.08, and 18.18 GHz, the negative group delay values achieve −5.4, −3.1, −1.18, and −1.14 ns, with |S21| values of −17.2, −20.5, −12.8, and −18.1 dB, respectively. Compared with the recently reported works, the proposed NGDC exhibits the largest number of operation frequency bands. Furthermore, it does not use lumped resistors and has miniaturized dimension.

Planar Tunable Negative Group Delay Circuit with Low Reflection Loss

Planar Tunable Negative Group Delay Circuit with Low Reflection Loss

A novel resonant‐type tunable group delay controller based on third‐order fully tunable topology

AbstractA novel resonant‐type group delay controller based on third‐order resonant topology with tunable central frequency and coupling coefficients is proposed. The coupling structure is realized by coupled line resonators loaded with two shunt capacitors for coupling coefficient tuning, and a series capacitor for resonant frequency tuning, then the group delay and working frequency can be tuned. The structure has the advantage of a large range of tunable coupling coefficients and breaks through the group delay tunable range of traditional delay circuits. The circuit is designed, simulated, and measured. The measurement shows that the group delay can be tuned from 5 to 20 ns with a tunable central frequency in the range of 0.8–1.05 GHz, and minimum ± 0.5 ns group delay bandwidth and −3 dB magnitude bandwidth of 12 MHz.

A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs

Continuous-time pipelined (CTP) ADCs have shown the potential to alleviate the challenges of discrete-time (DT) pipelined converters with Multi-GHz bandwidth, but have so far required an oversampling ratio (OSR) of at least 4. After elucidating the factors that limit CTP bandwidth, this paper presents a design methodology for near-Nyquist CTP ADCs. The delay circuit is optimized to match the ADC/DAC path in both its broadband magnitude response and phase. The residue filter response is optimized to prevent image signals from overloading the subsequent stage. We show that practical circuits can realize these optimized responses and extend the bandwidth of the CTP architecture to OSRs of 1.5-2.0, essentially equivalent to the OSR of DT converters when allowing for practical anti-aliasing. The direct path (i.e. delay) and the residue-amplifying filter circuits required for 3 GHz bandwidth are incorporated into a complete 4-bit 10 GS/s CTP ADC stage in a 28nm CMOS prototype. Simulation and measurement results confirm that CTP ADCs can operate at a near-Nyquist sampling rate with an OSR of 1.7.

A Commutated-LC RF Broadband Delay Circuit

This article presents a commutated-inductor–capacitor (commutated- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> ) or switched- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> circuit that acts as a radio frequency (RF) delay line. Thanks to its linear-periodically time-varying (LPTV) operation and fully passive implementation, it concurrently achieves long maximum delays, fine delay tuning steps, and wide instantaneous bandwidths while being low loss and highly linear. Unlike existing LPTV switched-capacitor broadband delays, the introduction of inductors in the proposed commutated- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> delay circuit provides a new degree of freedom, allowing it to operate at a much higher RF with a wider instantaneous bandwidth. A proof-of-concept prototype in a 65-nm CMOS process demonstrates a measured 1.3-GHz 3-dB bandwidth around a 4.3-GHz RF, i.e., a 30% fractional bandwidth, when clocked at 250 MHz. The measured maximum delay is 1.4 ns with a 23-dB loss and noise figure; this loss or noise is orders of magnitude lower compared with fully passive linear-time-invariant RF delay lines operating at a similar frequency with the same delay. The measured IIP3 is +16 dBm.

A Compact Dual-Band Differential Negative Group Delay Circuit With Wideband Common Mode Suppression

A compact dual-band differential negative group delay (DNGD) circuit with wideband common mode suppression is proposed. Two small 180° phase shift swap structures of double-sided parallel striplines (DSPS) are adopted to realize intrinsic wideband common-mode suppression. The dual-band DNGD characteristic is achieved by the DSPS coupled asymmetrically with two different-length open-circuited resonators. The DNGD times and center frequencies of the lower and upper bands can be tuned independently. To verify the proposed DNGD circuit topology, a prototype is designed, fabricated, and measured. From the measured results, DNGD times are −1.60 ns and −1.43 ns at the center frequencies of 1.227 GHz and 1.575 GHz, respectively. The differential insertion loss is lower than 3.55 dB, the differential return loss is larger than 13.3 dB and the common-mode suppression is over 30.8 dB in both DNGD bands.

A self‐packaged SCPW negative group delay circuit and its integration with power divider

In this article, a matched branch line-loaded negative group delay (NGD) circuit without resistor is presented firstly, and then an Wilkinson power divider with NGD characteristic is implemented by integrating the NGD circuit and the power divider by using self-packaged suspended coplanar waveguide (SCPW) technology. The self-packaged SCPW power divider with NGD characteristic has been fabricated, and the design has been demonstrated by measurement, which indicates that the proposed power divider with NGD characteristic has a measured signal attenuation (S21) of 10.92 dB, a S11 attenuation of 32.1 dB, an NGD time of −2.42 ns, and an isolation of no less than 39 dB at the center frequency, while simple circuit topology, self-packaging and compact circuit size have also been achieved.

A Hybrid True-Time and Phase-Delayed Approach for Millimeter-Wave Beam Steering

In this research study, a novel hybrid approach to beam steering based on the combination of true time delay and phase shift to enable continuous beam steering with minimal beam squint in wideband mm-wave transceivers is investigated. With modern high-speed communication links in the mm-wave spectrum requiring ever higher bandwidths, and losses increasing with frequency, there is a need for steerable arrays in mobile applications. This steering capability is commonly realized by phase shifters, which enable continuous beam direction control, but produce significant beam squint at large bandwidths or steering directions. An alternative is to use a time-delayed control, which resolves the squint issue but covers only a limited number of beam directions, producing considerable loss and being large in size. This research work presents the first 2-bit time delay stage operating above 200 GHz. In addition, a novel approach is described to enable broadband continuous beam control with minimal beam squint; this is achieved by combining the time delay circuit with a 90° vector-sum phase shifter. To prove the concept, the circuit is realized in a 130-nm SiGe Bipolar Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) technology. At 4.33 mW of dc power consumption, the small-signal gain is −8.6 dB at a 3-dB band of 220–250 GHz, resulting in 12.8% of relative bandwidth. The time delay stage provides coarse beam direction control with a maximum steering angle of 43.9° resulting from a maximum delay of 1.47 ps with a resolution of 0.39 ps. Across all tuning states, the root-mean-square delay error is less than 23.7 fs. The following phase shifter enables fine direction control while also compensating ±1.5 dB of gain variation resulting from the time delay. This is achieved while reducing the area consumption to half of what is required for comparable true time delay circuits. In a minimal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 1$ </tex-math></inline-formula> antenna array, this enables continuous beam direction control between ±54.6° while limiting the beam squint to less than 2.5°, equating to a more than 75% reduction in comparison to the common phase shift approach.

Acoustic travelling wave separation in the time domain using electronic time delay circuits and leaky recursion

Acoustic travelling plane wave separation is implemented in the time domain from the sound pressure signals of two closely spaced microphones using analog electronic circuits based on a leaky recursion formulation. The sound pressure and acoustic particle velocity signals at the midpoint between the microphones are estimated from delayed recursive expressions modified for stability by introducing mild loss recursion. The forward and backward travelling wave components are obtained electronically by simple linear combinations of the sound pressure and particle velocity signals. Two travelling wave separation circuits (TWSC) were designed, built, and evaluated from measurements in an acoustic test tube apparatus in the operational frequency range from 710 to 5,680 Hz. The two designs differ in the use of first- or second-order time delay electronic circuits, with performance of the first-order circuit degrading with increasing frequency. Experimental results for the second-order circuit show a travelling wave separation error of -30.4 dB in the operational frequency range, a travelling wave amplitude accuracy within ±0.1 dB in most of the frequency range, with an implementation that offers operation in real-time with low latency, and resilience to unknown initial conditions or similar errors during operation, with typical transient relaxation times of 2 ms, that can be made lower at the expense of reduced accuracy.

Wideband Flat Negative Group Delay Circuit With Improved Signal Attenuation

A novel wideband flat negative group delay (NGD) circuit with improved signal attenuation is proposed. The proposed negative group delay circuit (NGDC) is composed of three transmission lines and two parallel branches, which are consisted of two series transmission lines with a resistor linking to a T-type stub. The complete closed-form design equations are presented. For verification, an NGDC is designed, fabricated, and measured at the center frequency of 2.14 GHz. From the measured results, NGD time of −1.11 ns at the center frequency is obtained with an insertion loss of 9.75 dB and return loss of 22.3 dB. The flat-NGD bandwidth reaches 6.1% from 2.072 to 2.202 GHz with ±11.5% group-delay fluctuation.

A Novel Dual-Band Negative Group Delay Circuit With a Stepped-Impedance Structure

A novel dual-band negative group delay (NGD) circuit employing an active stepped-impedance structure is presented in this letter. A theoretical analysis on the dual-band NGD response of the proposed structure is presented. The characteristic impedances and phases of the transmission lines are calculated to implement the circuit’s I/O transmission function. This calculation is performed by defining the desired NGD values at two arbitrary frequencies as the operating condition. The theoretical analysis demonstrates that there is no dependence between the group delay (GD) values at different frequencies. Prototypes of the proposed circuit with the same or different GDs are designed, fabricated, and measured to demonstrate the performance of the proposed structure. The experimental results show that the proposed dual-band NGD circuit is capable of generating −1 ns GD at 0.7 and 1.3 GHz or different GDs (−0.3 and −2 ns). The corresponding maximum and minimum transmission gains are 2 and −8 dB, respectively.

Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current

A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0[Formula: see text]A) to 10 or 30[Formula: see text]A or else 50[Formula: see text]A in 10[Formula: see text]ns. Simulated in a 0.09-[Formula: see text]m CMOS process and power supply voltage ([Formula: see text]) of 1.1[Formula: see text]V, the proposed circuit in post-layout can operate from 435.5[Formula: see text]ps to 152.2[Formula: see text]ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5[Formula: see text]ps for NN and SS process corner, respectively, following a [Formula: see text]C change in temperature. But an abrupt high current [Formula: see text] pumped into the chip causes the voltage ([Formula: see text]) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp [Formula: see text] of 0–50[Formula: see text]A in 10[Formula: see text]ns for the two vector CBA happens to be around 5.0 and 4.4[Formula: see text]ps, respectively. The current ramp also generates power supply noise of 0.468[Formula: see text]V occurring close to the silicon chip. This, in turn, corresponds to a [Formula: see text] of 0.642[Formula: see text]V near the die, appearing to be much less than the required [Formula: see text] of 1.1[Formula: see text]V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642[Formula: see text]V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage.

Pre-Detection Sensing With Multistage Low-Pass Type Negative Group Delay Circuit

This paper reveals a fascinating pre-detection technique of sensor signals by means of counterintuitive negative group delay (NGD) electronic function. The sensor signal pre-detection technique is unconventionally developed thanks to the engineering of low-pass (LP) type NGD circuit. The NGD pre-detection basic principle is introduced. After topological description, the LP-NGD cell design method in function of negative time delay specification is formulated. An innovative analysis of time-advance property related to multi-stage LP-NGD cell is elaborated. To demonstrate the LP-NGD pre-detection technique feasibility, a proof of concept (POC) is designed with fabricated 3-stage LP-NGD printed circuit board (PCB) prototype integrating 4 LED detectors. The NGD pre-detection experimental setup is described. Extraordinary pre-detection with −0.5 s negative time propagation visible with LED on-lightning is demonstrated by considering a sinc pulse input signal. The developed NGD pre-detection technique can be useful in the future for the anticipation of industrial equipment damages and failure pre-detection sensor system in real-time.

Integrated refractive index sensor based on an AlN-PSiO2 hybrid plasmonic microdisk resonator.

In this paper, a microdisk resonator (MDR) based on an AlN-PSiO2 hybrid plasmonic waveguide (HPW) and its refractive index (RI) sensing characteristics are investigated. The plasmonic characteristics of the MDR based on the AlN-PSiO2 HPW (APHPW-MDR) in near-infrared wavelengths are studied by using the finite element method. Through the structure parameter optimizations, the propagation length (Lprop) of the APHPW-MDR is ∼165µm, which is ∼2.5 times as long as that of the MDR based on the AlN HPW (AHPW-MDR). The simulation results show that the quality factor (Q) and extinction rate (ER) of the APHPW-MDR are ∼621.3 and ∼30dB, respectively. The RI sensing sensitivity (S) of the RI sensor based on the APHPW-MDR is ∼276.6nm/RIU. The RI sensor based on the APHPW-MDR has wide application prospects in high-performance biochemical sensing, and it can also be used in integrated optical filters, modulators, switches, routers, and delay circuits.

Analysis of Septuple-Band NGD Circuit Using an E-Shaped Defected Microstrip Structure and Two T-Shaped Open Stubs

In this article, a compact distributed septuple-band negative group delay circuit (NGDC) is proposed and analyzed. It is mainly composed of a high–low–high step-impedance microstrip line with an E-shaped groove and two T-shaped open stubs. This NGDC was first simulated and then fabricated by using a conventional printed circuit board (PCB) process with the substrate of RO4350. To investigate the operational mechanism of the NGDC, an equivalent circuit, consisting of nine transmission lines, four series–parallel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> resonant circuits, and two T-type series <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> resonant circuits, has been developed and analyzed. It is found that the theoretical group delay characteristic calculated from the equivalent circuit agrees well both with the simulated data by using ADS as well as HFSS and with the experimental results. The measured seven NGD resonant frequencies occur at 2.03, 2.84, 8.14, 8.74, 13.0, 16.02, and 18.46 GHz, and the corresponding NGD values read −3.65, −3.04, −1.73, −3.23, −1.16, −1.20, and −1.47 ns. The dimensions of the presented passive NGDC are only 25 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times22$ </tex-math></inline-formula> mm without using any lumped components.

Reconfigurable negative group delay circuit with tunable group delay flatness

A reconfigurable negative group delay circuit (NGDC) with tunable group delay flatness is presented. The proposed NGDC is composed of an amplifier, three series resistors connecting with two transmission lines, two varactors, and a diode. By shorting different resistors through the diode, different negative group delay (NGD) times can be obtained. Two varactors are utilized to tune the flatness of the group delay. For verification, an NGDC is designed, fabricated, and measured at the center frequency of 1.0 GHz. The measured NGD time is tuned from −2.0 to −5.8 ns. The flat-NGD bandwidth varies from 2.2% to 8.8% with ±8% group-delay fluctuation. And the insertion loss varies from 6.5 to 13.8 dB.