Degradation Of Transistors Research Articles

A Novel Isolation Approach for GaN-Based Power Integrated Devices.

This paper introduces a novel technology for the monolithic integration of GaN-based vertical and lateral devices. This approach is groundbreaking as it facilitates the drive of high-power GaN vertical switching devices through lateral GaN HEMTs with minimal losses and enhanced stability. A significant challenge in this technology is ensuring electrical isolation between the two types of devices. We propose a new isolation method designed to prevent any degradation of the lateral transistor's performance. Specifically, high voltage applied to the drain of the vertical GaN power FinFET can adversely affect the lateral GaN HEMT's performance, leading to a shift in the threshold voltage and potentially compromising device stability and driver performance. To address this issue, we introduce a highly doped n+ GaN layer positioned between the epitaxial layers of the two devices. This approach is validated using the TCAD-Sentaurus simulator, demonstrating that the n+ GaN layer effectively blocks the vertical electric field and prevents any depletion or enhancement of the 2D electron gas (2DEG) in the lateral GaN HEMT. To our knowledge, this represents the first publication of such an innovative isolation strategy between vertical and lateral GaN devices.

The new approach of a simulation low dose rate radiation effects in bipolar integrated circuits

The model is proposed to explain the effects of low dose rate under the radiation influence in bipolar structures, taking into account the effects of subthreshold displacement in high-doped silicon layers. The base current degradation of bipolar transistor is determined of surface and displacement radiation effects in the near-surface base area. The conditions for the enhanced low dose rate sensitivity (ELDRS) in bipolar structures are shown. The presented results of the analysis allow us to explain most of the observed experimental results.

Deep insights into the mechanism of nitrogen on the endurance enhancement in ferroelectric field effect transistors: Trap behavior during memory window degradation

The nitridation process can significantly improve the quality of the interfacial layer and suppress the unrecoverable electron trapping of the interfacial states during cycling, which is the main cause of endurance enhancement. In this work, through in-depth analysis of defect behavior during memory window (MW) degradation in ferroelectric field effect transistors (FeFETs), it is found that the degradation of FeFET devices with SiON interfacial layer starts within the HZO layer, while the degradation process of FeFET devices with SiO2 interlayer initially begins at the interlayer and then penetrates into the HZO layer. First, the MW degradation processes of nitridation/non-nitridation devices are measured and compared. Moreover, through the extended measure-stress-measure method, three types of defects are defined and the defect behaviors including trapping kinetics and energy locations during degradation are systematically investigated. The mechanism of nitrogen on the endurance enhancement is finally revealed. These results are valuable to better understand the reliability issues of FeFET and pave the way for future process optimization.

Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters

Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing the data rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-rate architectures imposes tight constraints on clock signal quality, in particular its duty-cycle. Radiation degradation of transistors in the clock path causesduty cycle distortion (DCD), affecting the output signal quality of the HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is presented. It compensates forprocess voltage temperature (PVT)variations as well as radiation-induced duty-cycle distortion of the clock.

Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability

Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability

High-Energy Radiation Effects on Silicon NPN Bipolar Transistor Electrical Performance: A Study with 1 MeV Proton Irradiation.

This study investigates the degradation of the silicon NPN transistor's emitter-base junction, specifically the 2N2219A model, under both forward and reverse polarization. We examine the current-voltage characteristics under the influence of 1 MeV proton irradiation at various fluencies, which are 5.3×108,5.3×1010,5×1011,5×1012, and 5×1013 protons/cm², all conducted at 307 K. The experimental findings elucidate a pronounced dependency of diode parameters, including the reverse saturation current, series resistance, and the non-idealist factor, on the incident proton flow. This observation underscores that proton-induced degradation is primarily driven by displacement damage, while recorded degradation is predominantly attributed to the generation of defects and interfacial traps within the transistor resulting from exposure to high-energy radiation. Our findings indicate that the effects of irradiation align more closely with the compensation phenomenon in doping rather than its reinforcement.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors (TFTs), severe instabilities and even hard breakdown under high-current stress (HCS) become critical challenges. In this work, the triggering voltage of HCS-induced self-heating (SH) degradation is defined in the output characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) TFTs, and used to quantitatively evaluate the thermal generation process of channel donor defects. The fluorinated a-IGZO (a-IGZO:F) was adopted to effectively retard the triggering of the self-heating (SH) effect, and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F. The proposed scheme noticeably enhances the high-current applications of oxide TFTs.

Modeling Analysis of BTI-Driven Degradation of a Ring Oscillator Designed in a 28-nm CMOS Technology

With tightening reliability margins, product-level aging analysis is gradually gaining impetus and is set to become an integral part of the modern design flow. Increased emphasis is placed on the development of physics-based compact models for the phenomena responsible for transistor degradation and their integration into EDA environments. Commercial Process Design Kits (PDKs) of advanced technologies have also started to include compact models for transistor degradation along with a dedicated reliability simulation framework. In this work, we present a comprehensive study of the compact aging models in one such commercial PDK, with the help of extensive measurement data from individual devices as well as Ring Oscillators (RO). Then, we perform our own extraction of model parameter shifts from full Id-Vgs fitting of the measured BTI-stressed devices to gain insight into the modeling procedure adopted by the foundry. We finally use the parameters extracted thusly to investigate the impact of the time-0 and the time-dependent device-to-device variability on RO degradation.

Degradation-Sensitive Control Algorithm Based on Phase Optimization for Interleaved DC–DC Converters

As the use of interleaved DC–DC converters in electric vehicles (EVs) increases, research on reliability improvement is required. In the case of interleaved DC–DC converters, degradation occurs between transistors and capacitors. In particular, transistor degradation imbalances cause an increase in output capacitor RMS current, which increases power loss and accelerates capacitor degradation. This degradation affects system reliability by increasing thermal stress. In this paper, based on a degraded 2-leg interleaved DC–DC boost converter, research to reduce the converter’s output capacitor RMS current was conducted. The output capacitor RMS current according to the transistor degradation imbalance was analyzed. As a result, it was confirmed that the transistor degradation imbalance causes an increase in the capacitor RMS current. To address this issue, a phase optimization algorithm for reducing increased capacitor RMS current is presented in this paper. Next, the phase optimization algorithm is mathematically analyzed. Finally, its efficacy is proved through simulations and experiments.

High-Precision Fitting of Simulation Parameters for Circuit Aging Effect

To take the influence of the aging effect on circuit performance into account at the early design stage, it is necessary to establish an accurate aging simulation model. However, there is a great discrepancy in the reversely deduced MOSFET transistor degradation from the aging model. To deal with that problem, a method is proposed in this paper that establishes the conversion relationship between the simulation parameters and the degradation of MOSFET transistor parameters. The degradation values were converted into model parameters that characterize the aging effect in SPICE, and the results show that aging simulation accuracy was improved to within 0.1%, which would bring great convenience to circuit reliability simulation and analysis. Lastly, we analyze the aging effect on the ring oscillator circuit via the model.

The dependence of proton energy on the parametric degradation in silicon bipolar junction transistors

The effects of high total dose proton irradiation on the reliability of silicon NPN rf power bipolar junction transistor (BJT) were examined by subjecting to 1, 3, and 5 MeV protons in the dose range from 100 Krad to 100 Mrad. The electrical characteristics such as Gummel characteristics (IB, IC-VBE), excess base current (ΔIB = IBpost – IBpre), current gain (hFE), and output characteristics (IC-VCE), built-in potential (Vbi) and the effective doping concentration (Nd) were studied before and after irradiation. SRIM simulation was conducted to understand the range and energy loss of protons in the BJT structure. SRIM and experimental results infer that the proton irradiation at lower energy (1 MeV) was found to degrade the current–voltage(I-V) and capacitance–voltage (C-V) characteristics more severely than higher-energy (3 and 5 MeV) proton irradiation. Thermal annealing on irradiated devices was also conducted to study the parametric recovery of irradiated devices.

Temperature effects on the performance of ferroelectric FET with random grain phase variation for non-volatile memory application

We report the temperature effects on the performance of ferroelectric field-effect transistor (FeFET)-based non-volatile memory (NVM) considering random grain phase variation in the ferroelectric layer through simulation. Based on the FE temperature effect model that accounts for both the transistor and ferroelectric degradation, we demonstrate that: (1) at a certain temperature, the memory window (MW) decreases with pronounced effect on low threshold voltage shift and its variation increases as the FE phase decreases; (2) with the temperature increases, the MW decreases with pronounced effect on high threshold voltage shift. The random grain phase variation further exacerbates the MW distribution, thus degrading the sensing margin. These results may provide insights for device design of high-performance FeFET-based NVMs.

Reliability analysis based on the Wiener process integrated with historical degradation data

AbstractFor high‐reliability and long‐life electronic devices, reliability analyses based on degradation data with small sample sizes are an outstanding question. Recently, increasing attention has been paid to the abundant historical degradation data. Exploiting the information in these historical data efficiently and integrating them to benefit the current reliability analysis is an important issue. This study proposes a new integrating method for the historical and current degradation data based on the Wiener process by considering the consistency of failure mechanisms between the different batches of degradation data. Simulation studies show that the new method has superior reliability estimation, and is robust to the assumption of consistent failure mechanisms. Finally, the proposed method is used to analyze a real data set consisting of the metal‐oxide‐semiconductor field‐effect transistor (MOSFET) degradation data.

The Influence of Deep-Level Defects With Various Depths in SiO2 on Ionizing Damage

In this article, we analyzed the interaction mechanism between ionization and displacement defects in SiO2 using experimental and simulation techniques. In the experiment, the gate-controlled lateral p-n-p transistors (GLPNPs) were pretreated by He ions irradiation with different energies, which can create additional oxygen vacancy defects (Vo) at various depth ranges in SiO2. The pretreated GLPNPs were irradiated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays to analyze their response to ionization damage. It can be found that the introduction of additional deep Vo in SiO2 weakens the ionization damage of GLPNPs, and this weakening effect is heavily related to the depth of additional deep Vo. In addition, the TCAD simulation tool was used to investigate the mechanism by which the ionization damage is weakened with additional deep Vo depth. The simulation results show that as the additional deep Vo defect approaches the SiO2–Si interface, the additional deep Vo defect enhances the capture of the holes (or release of electrons), resulting in a decrease in hydrogenated Vo ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {Vo}\mathbf {H}_{\mathbf {2}}^{\mathbf {+}}$ </tex-math></inline-formula> ) concentration, which affects the release of protons and ultimately reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{\mathrm {it}}$ </tex-math></inline-formula> . Based on the above mechanism, it would be helpful to accurately evaluate the electrical characteristics degradation of bipolar transistors in complex space environments.

Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses

In this study, a quantitative analysis was conducted on the effects of channel width on electrical performance degradation induced by self-heating stress (SHS) in top-gate self-aligned coplanar indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). From the transfer and capacitance-voltage curves obtained before and after SHS, we revealed that the electrical performance of the TFT was nonuniformly degraded along the channel length direction and the degree of this degradation was more significant in TFTs with a wider channel width. The threshold voltage shift (ΔVSUBTH/SUB) under SHS in the fabricated IGZO TFT was mainly attributed to the increase in the density of shallow donor states and acceptor-like deep states in the IGZO active region and electron trapping into the fast and slow traps in the SiOSUBX/SUB gate dielectric. In addition, we conducted a decomposition of the SHS-induced ΔVSUBTH/SUB originated from each degradation mechanism using the subgap density of states-based ΔVSUBTH/SUB decomposition technique for TFTs with different channel widths. Although every ΔVSUBTH/SUB from each degradation mechanism increased as the channel width increased, increased electron trapping into the slow trap in the SiOSUBX/SUB gate dielectric was the dominant reason for the larger ΔVSUBTH/SUB under SHS in IGZO TFTs with a wider channel width.

An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

Temporal degradation of transistors due to aging causes mismatch in the current mirror, a matching-critical building block of current digital to analog converters (IDACs). This mismatch induces non-linearity in IDAC behavior and can cause nonmonotonicity in the worst case. This paper performs an application-driven analysis of IDAC aging within a feed-forward equalizer (FFE) context. The work first models the effect of aging-induced mismatch over IDAC performance metrics and analyzes the performance shifts of IDACs over different topologies and input distributions. Next, the work illustrates how IDAC aging affects FFE behavior and presents novel schemes for FFE calibration to counter the impact of IDAC aging effectively.

Environment-Dependent Radiation Tolerance of Graphene Transistors under Proton Irradiation.

Electronic devices based on two-dimensional materials are promising for application in space instrumentation because of their small size and low power consumption, and irradiation tolerance of these devices is required because of the existence of energetic particles in aerospace conditions. We investigate the performance degradation of graphene field effect transistors (GFETs) with 3 MeV protons by using an in situ irradiation facility. Our results indicate that GFET performance degraded severely at the ion fluence of 8 × 1011 cm-2. Surprisingly, although the performance of the proton-irradiated GFETs is difficult to recover in vacuum, it can nearly completely recover within hours when the GFET is moved into an air environment, indicating that the performance change is due to the charge accumulation in SiO2 under proton irradiation rather than the lattice damage of graphene. Our results have great importance for the application of 2D devices in aerospace and other radiative environments.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The low temperature poly-Si thin-film transistors (LTPS TFTs) have been extensively applied in the AMLCD and AMOLED due to their high carrier’s mobility and driving currents, and the ability to integrate the driving circuits onto the same substrate. The main mechanisms causing the degradation of the LTPS TFTs under bias stress are: hot carrier effect and self-heating effect. In this study, the degradation and recovery phenomena of the LTPS TFTs stressed by the hot carrier effect conditions would be systematically investigated. The device structures used in this study are n-channel LTPS TFTs with different lengths of lightly doped drain (LDD).First, we simultaneously apply a small positive DC voltage, approximately the threshold voltage plus 1V (Vth+1= +3 V), to the gate terminal and a large positive DC voltage (+12 V) to the drain terminal of the LTPS TFTs with three different LDD’s lengths. These stressing conditions would cause the TFTs operated in the saturation region, so that the channel is pinched off. And the electrons would be accelerated by a large transverse electric field when they drift from the source terminal to the drain one. The energetic electrons would impact the lattices of the channel and the interface between the gate dielectric and the channel near the drain terminal, causing the defect states and electron-hole pair generation. Few of the carriers with enough energy to overcome the energy barrier of gate dielectric would be trapped by the defects in it. The hot carrier effect causes the degradation of the TFTs devices, including the decrease of ON current and carrier mobility and the increase of OFF current, but less degradation of the threshold voltage and subthreshold swing. After the bias stressing, the resting time is added to investigate the recovery phenomena. The difference in the amount of degradation and the location of defects would cause the different recovery ratio. After the end of bias stressing, all of the terminals are not applied with any voltages in the resting periods. The electrons and holes generated in the channel near the drain terminal would recombine, and the defect states generated by the hot carrier impact slightly reduce, which causes the recovery phenomena of the degraded transistors.Then, we apply a small AC voltage (0 ~ +3 V) to the gate terminal and a large positive DC voltage (+12 V) to the drain one at the same time. This mode of bias stressing conditions is closer to the real operating mode of the TFTs in the driving circuits. From the experimental data, it could be found that there is no significant difference in the degradation of the TFTs under different frequency of AC signals applied on the gate. But the recovery ratio tends to gradually increase as the frequency increasing.Finally, a small positive DC voltage (+3 V) is applied to the gate terminal, and a large AC voltage (0 ~ +12 V) to the drain one at the same time. From the experimental data, it could be found that with the increase of AC signal frequency, the degradation of the TFTs decreases, but the recovery ratio of the TFTs increases due to the reduction of the effective stressing time in one period. As compared to the results of all stressing conditions, the TFTs, both of the gate and drain terminals applied with DC voltages, exhibit the largest degradation ratio but the least recovery one. However, the TFTs, as the gate terminal applied with DC voltages and drain one with AC voltage, exhibit the less degradation ratio but the largest recovery one.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The degradation and recovery phenomena of n-type LTPS TFTs stressed at hot carrier effect region under various bias conditions are investigated. The devices with longer LDD’s length demonstrate less degradation ratio but more recovery ratio, because of the lower transverse electric field. As the AC signals are applied to the gate terminal, the degradation of devices shows no significant dependence of AC signal frequency, but the recovery ratio displays the similar trends as AC signal frequency changing. However, as the AC signals are applied to the drain terminal, the degradation of devices shows very significant dependence of AC signal frequency. The higher the AC signal frequency is, the less degradation the devices show, but the recovery ratio displays the similar trends as AC signal frequency changing. From the results of all stressing conditions, the LTPS TFTs stressed with DC voltages exhibit the largest degradation ratio but almost the least recovery one.

An Extraction Method for Mobility Degradation and Contact Resistance of Graphene Transistors

The intrinsic mobility degradation coefficient, contact resistance and the transconductance parameter of graphene field-effect transistors (GFETs) are extracted for different technologies by considering a novel transport model embracing mobility degradation effects within the charge channel control description. By considering the mobility degradation-based model, a straightforward extraction methodology, not provided before, is enabled by applying the concept of the well-known Y-function to the \textit{I-V} device characteristics. The method works regardless the gate device architecture. An accurate description of experimental data of fabricated devices is achieved with the underlying transport equation by using the extracted parameters. An evaluation of the channel resistance, enabled by the extracted parameters here, has been also provided.