Degradation Of Transistors Research Articles

Assessment of TID Effect of FRAM Memory Cell Under Electron, X-Ray, and Co- $60~\gamma $ Ray Radiation Sources

This paper investigates the total ionizing dose (TID) effect of the memory cell of the ferroelectric random access memory (FRAM) under electron, X-ray, and Co- $60~\gamma $ ray radiation sources. An electron accelerator and an X-ray microbeam from synchrotron, which are used to simulate the given radiation environments, offer local irradiation on the FRAM memory cell. In addition, the Co- $60~\gamma $ ray source provides global irradiation on the full chip of FRAM. The FRAM memory cell is proved to have a lower failure threshold for TID effect than the ferroelectric thin-film capacitor due to the performance degradation of nMOS transistor in memory cell. The failure phenomenon is studied according to the experimental results of different radiation sources, and the failure mechanism is discussed based on the technology and the characteristics of FRAM memory cell in circuit-level. The difference of device performance is also analyzed for electron irradiation and X-ray irradiation.

Compact Modeling of Dynamic MOSFET Degradation Due to Hot-Electrons

A trap-density-based compact model of dynamic metal-oxide semiconductor field-effect transistor degradation due to hot electrons is reported, for which model parameters are extractable from measured 1/ ${f}$ noise properties. It is observed that the deep trap-state increase is dominant for the degradation and approaches its maximum under long accelerated-stress duration. A key modeling concept is the explicit inclusion of the extracted stress-condition-dependent trap density in the Poisson equation, which is solved iteratively. The developed model correctly predicts actual dynamic degradation of the measured I-V characteristics, that is, trap density increase during stress application, without the disadvantage of longer simulation times. The reported model can automatically reproduce not only the threshold-voltage shift, but also the degradation of the complete ${I}$ – ${V}$ characteristics and all other observable effects caused by the carrier trapping, without any additional model-parameter fitting for each of these effects.

Effects of plasma treatment on the electrical reliability of multilayer MoS2 field-effect transistors

Electric stability and recovery properties of multilayer molybdenum disulfide (MoS2) field-effect transistors (FETs) were investigated by plasma treatment via inductively coupled plasma and polymethyl methacrylate (PMMA) passivation. Plasma treatment is proposed as an efficient method for cleaning the surface of MoS2. The results indicate that performance degradation of MoS2 field-effect transistors owing to oxygen absorption is largely restored by the plasma treatment. It is also shown that PMMA passivation (7% chlorobenzene) degrades the performance of the MoS2 FET. The performance degradation of the device can be restored by the plasma treatment. It is suggested that high-density plasma treatment with minimized damage to the surface can be an efficient method of surface cleaning. These findings are especially important for the nanolithography and nanodevice fabrication of two-dimensional devices made of MoS2, graphene, etc., using PMMA resistors.

3-D TSV Six-Die Stacking and Reliability Assessment of 20- $\mu$ m-Pitch Bumps on Large-Scale Dies

3-D integration typically involves multiple chips stacking with large numbers of interconnections within each chip. There are several fundamental technology challenges that need to be addressed in order to realize 3-D integration, such as Cu through-silicon via (TSV) expansion, transistor degradation or open failures on Cu contamination, microbump stress, and so on. The reliability issues on TSV and microbumps are very critical not only for a stacked chip package, but also during wafer-level processes. In this paper, the authors successfully stacked six chips with a thickness of 50 $\mu \text{m}$ and assessed their reliability. Each chip consists of 122054 bumps with a bump diameter of $10~\mu \text{m}$ and a pitch of 20 $\mu \text{m}$ . These bumps were built directly on TSVs, which have a diameter of $5~\mu \text{m}$ . Measured electrical resistance is well matched with calculated electrical resistance. Finally, this paper presents the reliability results of the 3-D IC packages that are embedded in molding compound.

Comparison of Gain Degradation and Deep Level Transient Spectroscopy in pnp Si Bipolar Junction Transistors Irradiated With Different Ion Species

We studied the effect of light ion and heavy ion irradiations on pnp Si BJTs. A mismatch in DLTS deep peak amplitude for devices with same final gain but irradiated with different ion species was observed. Also, different ions cause different gain degradation when the DLTS spectra are matched. Pre-dosed ion-irradiated samples show that ion induced ionization does not account for the differences in DLTS peak height but isochronal annealing studies suggest that light ions produce more VP defects than heavy ions to compensate for the lack of clusters that heavy ions produce. The creation of defect clusters by heavy ions is evident by the higher content of E4 and ${\mathrm {V}}_{2}^{\ast}$ defects compared to light ions.

High Gamma Ray Tolerance for 4H-SiC Bipolar Circuits

A high gamma radiation hardness of 4H-SiC circuits is performed. The OR NOR circuits are based on emitter coupled logic (ECL), using integrated bipolar NPN transistors. Gain degradation in individual bipolar junction transistors (BJT) is minimal up to a dose of 38 Mrad (SiO2), but for the dose of 332 Mrad (SiO2) a degradation of 52% is observed. The SiC BJTs show higher radiation hardness than existing Si-technology and high stability under temperature stress. It is proposed that the oxide charge-dominated recombination is the key base current recombination mechanism contributing to gain degradation. An improvement in the gain is seen after annealing at 400 °C for 1800 s due to the possible annealing of some of the oxide defects contributing to the oxide charge.

Effect of Rising Edge during Dynamic Stress With Duty Ratio in Amorphous InGaZnO Thin Film Transistors

We investigated the effects of rising edge during positive unipolar dynamic stress and bipolar dynamic stress under darkness and illumination with duty ratio D of dynamic stress from 1 to 50%. Threshold voltage shift ${\rm{\Delta}}V_{\rm{th}}$ increased with effective time $t_{\rm{eff}}$ as the product of stress duration and D . ${\rm{\Delta}}V_{\rm{th}}$ was higher during bipolar stress than during positive unipolar stress and under low D than at high D . Degradation of amorphous InGaZnO thin film transistor is related to the number and amplitude of rising edges. We suggest that an additional degradation under dynamic stress is originated from high electric field in channel region at rising edge.

(Invited) Toward an Understanding of Defects and Device Reliability in GaN Hemts

GaN device reliability has become a major factor in technology acceptance for various electronics applications including high radiation and space applications. GaN’s properties make it ideal for a variety of harsh conditions including high energy particle radiation, high power RF biasing, high temperature, and simultaneous combinations of these stressors. Understanding how trapping behavior impacts the electrical characteristics and how defects form or are activated with these various stressors is important to predicting lifetime and end of life performance and approaches to reduce the degradation rate, improve the radiation hardness, etc. This work explores different modes of GaN high electron mobility transistors (HEMT) degradation when subjected to proton irradiation and electrical stressing. Specific trap states associated with different stress conditions are revealed using conventional and HEMT-based deep level optical spectroscopy (DLOS) and deep level transient spectroscopy (DLTS) methods. These trap characterization techniques provide quantitative information about degradation-limiting traps that can exist anywhere within the device bandgap profile and can be distributed within specific regions of the device structure. In addition, using the newly developed scanning-DLTS, we will show the ability to quantitatively map specific defects on the nanometer scale to identify how defects are related to specific microstructure. Multiple types of AlGaN/GaN HEMTs were characterized in a systematic fashion using conventional, HEMT-based, and scanning-DLTS and DLOS before and after the application of RF switching, high voltage switching and irradiation. Overall, radiation is found to form defects that primarily impact the threshold voltage where shallower traps cause dynamic threshold voltage VT instabilities and deeper traps cause static VT shifts. In particular, proton irradiation is found to increase the concentration of traps at EC-1.3 eV and EC-3.28 eV in the GaN buffer, which appear to be responsible for large and persistent VT shifts in GaN HEMTs, and a state at EC-0.72 eV in the GaN buffer that separately correlates with an increase in dynamic VT instability. The RF accelerated life testing (ALT) has led to different degradation pathways in different generations of HEMTs and different vendors but has consistently been in the drain access region where the electric fields are maximized, which is quite different than the radiation-induced degradation. Early generations consistently showed correlation of the RF output power with the concentration of the EC-0.57 eV level, which we have recently mapped with scanning-DLTS to directly correlate the EC-0.57 eV level with edge dislocations and Fe doping. Newer generations have degraded due to deeper, near mid-gap defects indicating that several degradation mechanisms are possible in GaN HEMTs and they evolve as the materials and device designs are improved. Semi-on DC ALT exhibits degradation somewhat different to RF ALT where the degradation is still due to defects in the drain access region but the traps responsible are different indicating that different testing mechanisms may not be predictive of actual degradation in some cases. The use of DLOS and DLTS to track the activation of these defects will be shown as essential to accurately determine exact degradation mechanisms to establish accurate predictive reliability models and guidelines for improved end of life material and device designs.

Deep traps and instabilities in AlGaN/GaN high electron mobility transistors on Si substrates

Deep traps were studied in multiple-finger AlGaN/GaN transistors with broad periphery by means of current–voltage and capacitance–voltage characteristics, reverse deep level transient spectroscopy, deep level transient spectroscopy with electrical (DLTS) and optical DLTS injection, and current DLTS (CDLTS) with gate voltage and drain voltage pulsing. Deep electron traps with activation energies of 0.25, 0.36, 0.56, and 0.8–0.9 eV are found to be responsible for variations in threshold current with applied gate bias. These traps also give rise to current transients observed at different temperatures in CDLTS. The 0.25 and 0.56 eV centers are most likely located at the AlGaN/GaN interface. The 0.25 eV state is believed to be nitrogen vacancy-related, the 0.36 eV level is of unknown origin, the 0.56 eV level is likely due to point defects enhanced in the presence of dislocations, and responsible for low luminescence efficiency of nonpolar n-GaN and for degradation of GaN transistors and light-emitting diodes and light-emitting diodes, while the 0.8 eV-level has been attributed to either interstitial Ga or N. Hole-trap-like relaxations in CDLTS were observed at temperatures higher than ∼300 K and attributed to hole traps near Ev + 0.9 eV located in the buffer layer. These have previously been assigned to either gallium vacancy-oxygen acceptor complexes (VGa-O)2− or carbon on nitrogen site acceptor (CN−) complexes. These results show that the stability of GaN-based high electron mobility transistors on Si is still dominated by the high concentration of point defects present in the material.

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeOx/Al2O3 gate dielectrics

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal–oxide–semiconductor field-effect-transistors (MOSFETs) with GeOx/Al2O3 gate stacks. It is found that the mobility increases with greater GeOx thickness (7.8–20.8 Å). The physical origin of this mobility dependence on GeOx thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeOx/Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeOx/Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeOx are found to be negligible. The density of the interfacial charge is +3.2 × 1012 cm−2 at the GeOx/Ge interface and −2.3 × 1012 cm−2 at the Al2O3/GeOx interface. The electric dipole at the Al2O3/GeOx interface is found to be +0.15 V, which corresponds to an areal charge density of 1.9 × 1013 cm−2. The origin of this mobility dependence on GeOx thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeOx interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeOx interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.

Correlation of proton irradiation induced threshold voltage shifts to deep level traps in AlGaN/GaN heterostructures

The impact of proton irradiation on the threshold voltage (VT) of AlGaN/GaN heterostructures is systematically investigated to enhance the understanding of a primary component of the degradation of irradiated high electron mobility transistors. The value of VT was found to increase monotonically as a function of 1.8 MeV proton fluence in a sub-linear manner reaching 0.63 V at a fluence of 1 × 1014 cm−2. Silvaco Atlas simulations of VT shifts caused by GaN buffer traps using experimentally measured introduction rates, and energy levels closely match the experimental results. Different buffer designs lead to different VT dependences on proton irradiation, confirming that deep, acceptor-like defects in the GaN buffer are primarily responsible for the observed VT shifts. The proton irradiation induced VT shifts are found to depend on the barrier thickness in a linear fashion; thus, scaling the barrier thickness could be an effective way to reduce such degradation.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200nm and 500nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Fault prognostic of electronics based on optimal multi-order particle filter

The accurate fault prediction is of great importance in electronics high reliability applications for condition based maintenance. Traditional Particle filter (TPF) used for fault prognostic mainly uses the first-order state equation which represents the relationship between the current state and one-step-before state without considering the relation with multi-step-before states. This paper presents an optimal multi-order particle filter method to improve the prediction accuracy. The multiple τth-order state equation is established by training Least Squares Support Vector Regression (LSSVR) via electronics historical failure data, the τ value and LSSVR parameters are optimized through Genetic Algorithm (GA). The optimal τth-order state equation which can really reflect electronics degradation process is used in particle filter to predict the electronics status, remaining useful life (RUL) or other performances. An online update scheme is developed to adapt the optimal τth-order state transformation model to dynamic electronics. The performance of the proposed method is evaluated by using the testing data from CG36A transistor degradation and lithium-ion battery data. Results show that it surpasses classical prediction methods, such as LSSVR, TPF.

Identification of the degradation state for condition-based maintenance of insulated gate bipolar transistors: A self-organizing map approach

This paper presents an approach for the detection of the degradation onset and the identification of the degradation state of industrial components with inhomogeneous degradation behaviors due to the effects of multiple, possibly competing, degradation mechanisms and non-stationary operational and environmental conditions. The novelty of the approach is the use of dedicated Self-Organizing Maps (one for each component): each Self-Organizing Map is trained using data describing the component healthy behavior and a degradation indicator is defined by the distance between the test measurement and the Self-Organizing Map best matching unit. A case study regarding Insulated Gate Bipolar Transistors used in Fully Electrical Vehicles is considered. Data collected in experimental accelerated aging tests are used. The proposed approach is shown able to detect the initiation of the Insulated Gate Bipolar Transistors degradation process and to anticipate the component failure.

Radiation-induced 1/f noise degradation of PNP bipolar junction transistors at different dose rates**Project supported by the National Natural Science Foundation of China (Grant Nos. 61076101 and 61204092).

It is found that ionizing-radiation can lead to the base current and the 1/f noise degradations in PNP bipolar junction transistors. In this paper, it is suggested that the surface of the space charge region of the emitter-base junction is the main source of the base surface 1/f noise. A model is developed which identifies the parameters and describes their interactive contributions to the recombination current at the surface of the space charge region. Based on the theory of carrier number fluctuation and the model of surface recombination current, a 1/f noise model is developed. This model suggests that 1/f noise degradations are the result of the accumulation of oxide-trapped charges and interface states. Combining models of ELDRS, this model can explain the reason why the 1/f noise degradation is more severe at a low dose rate than at a high dose rate. The radiations were performed in a Co60 source up to a total dose of 700 Gy(Si). The low dose rate was 0.001 Gy(Si)/s and the high dose rate was 0.1 Gy(Si)/s. The model accords well with the experimental results.

Hydrophobic dielectric surface influenced active layer thickness effect on hysteresis and mobility degradation in organic field effect transistors

Effect of active layer thickness, influenced by the hydrophobic dielectric surface, on the performance of copper phthalocyanine based organic field effect transistors (OFETs) was studied. While charge carrier mobility was found to be highest for an optimum thickness of 30 nm, hysteresis and threshold voltage shift were found to be minimum for 15 nm thick film which is attributed to the excess availability of photogenerated carriers, especially close to the dielectric/semiconductor interface, as this thickness is within the exciton quenching length in organic semiconductors. But prolonged bias stress resulted in larger decay in drain current for higher thickness indicating the dominant role played by the larger grain boundary density in the increased volume. These results were found to be different from that on unmodified SiO2 dielectric with higher surface energy and were suggested to be caused by the 3D growth mode of CuPc films on the hydrophobic surface. Mobility degradation at higher gate voltages also exhibited a dependence on the active layer thickness which was tuned by the hydrophobic surface induced growth mode at the dielectric/semiconductor interface.

Reduction of Hot Carrier Degradation of FinFETs Due to Short-Pulse Stress

Hot carrier degradation of field effect transistors is shown to be reduced when the transistors are subjected to very short pulses. A technique for applying short gate pulses to devices and measuring the change in drain current is described. Applied to FinFETs fabricated on SOI substrates, measurements show that the degradation can be almost three times less than that of DC conditions when the pulses are of nanosecond duration. This reduction is explained to be the result of reducing the self-heating of the devices during hot carrier stress.

Influence of hole and electron trapping on gate field dependent mobility and its degradation in organic field effect transistors

Influence of hole and electron trapping effect on the gate field dependence of mobility, especially degradation at higher gate voltages, in organic field effect transistors is identified. Extent of mobility degradation was found to be dependent on the starting value of the gate voltage sweep. Both electron and hole trap concentrations are found to cause degradation in mobility with the former dominating over the latter. Significant increase in hole trap concentration causes slow increase in mobility for a certain span of gate voltage before shifting the onset point of degradation to much higher gate voltages. The interplay between the trap density, carrier density, mobility and the effective gate field decides the extent of degradation. Reduction of both hole and electron trap concentration by passivating the trap centres on the dielectric surface with suitable polymers resulted in constant mobility at higher gate voltages.

Evidence for causality between GaN RF HEMT degradation and the EC-0.57 eV trap in GaN

The degradation of industry-supplied GaN high electron mobility transistors (HEMTs) subjected to accelerated life testing (ALT) is directly related to increases in concentrations of two defects with trap energies of EC-0.57 and EC-0.75eV. Pulsed I-V measurements and constant drain current deep level transient spectroscopy were employed to evaluate the quantitative impact of each trap. The trap concentration increases were only observed in devices that showed a 1dB drop in output power and not the result of the ALT itself indicating that these traps and primarily the EC-0.57eV trap are responsible for the output power degradation. Increases from the EC-0.57eV level were responsible for 80% of the increased knee walkout while the EC-0.75eV contributed only 20%. These traps are located in the drain access region, likely in the GaN buffer, and cause increased knee walkout after the application of drain voltage.

Impact of Negative Bias Temperature Instability on 6T CMOS SRAM Cell Performance

This paper presents the effect of negative bias temperature instability (NBTI) on a 6T CMOS SRAM cell and a technique to correct the NBTI induced error. The effect of NBTI on the generation of interface traps and Ids-Vgs characteristics is analyzed. The degradation of static noise margin and PMOS transistor’s Vth with increase in simulation time is analyzed in SRAM cell. Threshold voltage degradation is simulated at two different technologies and it is found that NBTI degradation is prominent in lower technology nodes. As memories occupy the maximum area on a chip, thus, more robust SRAM design is required for high reliability of SRAM cell. MOSFET reliability analysis (MOSRA) model is used to simulate the effects of Bias Temperature Instability and hot carrier injection. Error introduced because of NBTI is corrected using a bit flipping technique.