Electron Mobility Degradation Research Articles

Investigation of Nano-Heat-Transfer Variability of AlGaN/GaN-Heterostructure-Based High-Electron-Mobility Transistors

The aim of this work is to propose an electrothermal model for predicting the electron mobility, the effective thermal conductivity, and the operating temperature of AlGaN/GaN HEMT devices. The suggested model comprises an enhanced ballistic-diffusive model (BDE) coupled with a drift-diffusion model (D-D). Furthermore, the given model considers total electron mobility, which depends on mobility degradation caused by phonon interactions, surface imperfections, and carrier mobility inside the bulk GaN material. The model is validated based on available experimental and numerical results, and good concordance is observed. It is found that the degradation of the drain current is due to electron mobility and effective thermal conductivity degradation. The output characteristic’s degradation due to changing device temperature is analyzed. We demonstrate that for gate biases of −1 V, 0 V, and 1 V, operating temperatures of 390 K, 470 K, and 570 K are obtained when the drain currents are 0.1 A, 0.24 A, and 0.38 A, respectively. Furthermore, we demonstrate that the temperature is maximal in the active region. The temporal temperature evolution presents the same trends with the same amplitude compared to the experimental data, and the error does not exceed 5%.

Optimization of vertically stacked nanosheet FET immune to self-heating

The self-heating effect (SHE) is one of the major challenges of ultra-scaled devices such as stacked nanosheet field effect transistor (SNSHFET) for sub 7 nm technology. The DC performance metrics of vertically SNSHFET are investigated and quantified against various geometrical parameters in the perspective of self-heating. Impact of self-heating is higher for larger gate and supply voltages. An average electron velocity reduction of 25 × 103 m/s and average electron mobility degradation of 242 cm2 V−1s−1 with SHE is observed for 5 nm thickness and 50 nm wider nanosheet. The increase in nanosheet width (WNSH) and thickness (tNSH), enhances device lattice temperature (TL) and other impediments. The results shows for the optimized device geometry, the SNSHFET exhibits better performance with immune to self-heating.

Impact of oxygen in electrical properties and hot-carrier stress-induced degradation of GaN high electron mobility transistors* *Project supported by the National Natural Science Foundation of China (Grant No. 62104167), the Natural Science Foundation of Jiangsu Province, China (Grant Nos. BK20210863 and BK20180966), and by Qing Lan Project of Jiangsu Province, China.

The role of the oxygen in AlGaN/GaN high electron mobility transistors (HEMTs) before and after semi-on state stress was discussed. Comparing with the electrical characteristics of the devices in vacuum, air, and oxygen atmosphere, it is revealed that the oxygen has significant influence on the electric characteristics and the hot-carrier-stress-induced degradation of the device. Comparing with the situation in vacuum, the gate leakage increased an order of magnitude in oxygen and air atmosphere. Double gate structure was used to separate the barrier leakage and surface leakage of AlGaN/GaN HEMT it is found that surface leakage is the major influencing factor in gate leakage of SiN-passivated devices before and after semi-on state stress. During semi-on state stress in the oxygen atmosphere, the electric-field-driven oxidation process promoted the oxidation of the nitride layer, and the oxidation layer in the SiN/AlGaN interface leads to the decreasing of the surface leakage.

Antidote-induced armchair graphene nanoribbon based resonant tunneling diodes

Resonant tunneling phenomena are explored using armchair graphene nanoribbon (AGNR), which eliminates the lattice mismatch and electron mobility degradation problems of conventional heterostructure resonant tunneling diodes (RTDs). Eight antidote topologies are proposed in this paper. These antidote topologies significantly increase or decrease the band gap of AGNR. Both double barrier quantum well and single barrier quantum well structures have been achieved by putting the antidote-induced AGNRs and pristine AGNRs. A numerical approach with a tight binding model and non-equilibrium Green’s function formalism has been used to simulate the quantum phenomena of the device. Current–voltage characteristics of these proposed RTDs show a high peak to valley ratio and low power dissipation with respect to different antidote topologies. Channel length variation effects are investigated in the proposed RTDs, and it is found that the peak to valley ratio, valley current, valley voltage, and power dissipation can be improved by tuning the channel length. These graphene-based RTDs are easy to fabricate and offer more flexibility in terms of peak to valley ratio, valley current, valley voltage, and power dissipation.

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

We have systematically examined electrical characteristics of ultra-thin body (UTB) (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) fabricated by the smart-cut process and have compared their electrical properties with those of (100) ones. The (111) GOI thickness was varied from 29.4 to 7.3 nm. The normal MOSFET operation of a 7.3 nm-thick (111)-oriented GOI nMOSFET has been demonstrated with a reasonable ON/OFF ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> . However, degradation in the effective electron mobility and subthreshold swing (SS) of the (111) GOI nMOSFETs with decreasing the GOI thickness ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOI</sub> ) was observed. Raman analyses and electrical characteristics of GOI nMOSFET under back-gate operation has suggested that a high interface state density at (111) GOI/buried oxide interfaces as well as low GOI film quality near the back interfaces can be an origin of this degradation of the electrical properties with thin body channels.

Simulation Study on the Optimization and Scaling Behavior of LDMOS Transistors for Low-Voltage Power Applications

We present a systematic investigation of device optimization for laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors in terms of subthreshold leakage current, breakdown voltage, and ON-resistance for low-voltage ( $10\boldsymbol {^{-13}}\text{A}/\boldsymbol {\mu }\text{m}$ while maintaining a breakdown voltage exceeding 10 V for channel lengths down to 10 nm. Interestingly, we find an optimal ON-resistance for a channel length of 40 nm, while for shorter channel lengths the ON-state resistance increases with decreasing channel length. The increasing resistance for shorter channels is caused by electron mobility degradation as a result of an increasing body doping, needed to limit the leakage current. The optimal channel length presents a limit to conventional scaling of LDMOS devices, commonly used in low-voltage power applications.

On/Off Boundary of Photocatalytic Activity between Single- and Bilayer MoS2.

Molecularly thin two-dimensional (2D) semiconductors are emerging as photocatalysts owing to their layer-number-dependent quantum effects and high charge separation efficiency. However, the correlation among the dimensionality, crystallinity, and photocatalytic activity of such 2D nanomaterials remains unclear. Herein, a Ag photoreduction technique coupled with microscopic analyses is employed to spatially resolve the photocatalytic activity of MoS2 as a model catalyst. Interestingly, we find that only monolayer (1L)-MoS2 is active for a Ag photoreduction reaction. The photocatalytic activity of 1L-MoS2 is enhanced by a built-in electrical field originated from the MoS2/SiO2 interface, instead of by the specific surface structure and quantum electronic state of 1L-MoS2. Furthermore, we observe photocatalytic active sites to be geometrically distributed on triangular 1L-MoS2 crystals, wherein the Ag particles are preferentially deposited on the outermost zigzag edges and defective inner parts of the triangular grains. The degradation of photocatalytic activity and electron mobility with the formation of Mo(VI) species indicates that the species inhibit the in-plane diffusion of the photogenerated electrons to the reductive sites. The monolayer-selectivity, activation, and inactivation mechanisms, unveiled in this work, will offer future directions in designing 2D nanophotocatalysts.

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a pre-determined leakage current suitable for low-voltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the on-resistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

Adaptive Body Biasing Circuit for Reliability and Variability Compensation of a Low Power RF Amplifier

This paper presents a simple compensation biasing circuit to enhance the reliability and variability of the low-power radio-frequency (RF) amplifier. The compensation function is achieved through a threshold voltage adjustment, which is realized by an adaptive varying body voltage of power amplifier transistors. The proposed circuit effectively preserves the power amplifier performance over a wide level range of output power under threshold voltage shift and electron mobility degradation. At the 0.63 dBm output power level, the sensitivity of the normalized efficiency of the power amplifier with the proposed compensation circuit under 0.16% threshold voltage shift and 0.16% mobility variations decreases as nearly 6.7 times and 2 times compared to the power amplifier without the compensation circuit, respectively. The operational principle of this structure is studied by deriving the analytical equations. The post-layout simulation results in the 180-nm RF complementary metal–oxide–semiconductor process are obtained and verify the proposed circuit effectiveness.

Ionic-Strength Dependence of Electron Mobility of Back-Gate Bilayer MoS2 FETs in Aqueous Electrolyte Solutions

In the past few years, atomically thin layered semiconductor materials have attracted numerous interest because of the potential of using those materials to establish liquid–semiconductor sensor systems towards next-generation biological/chemical sensing applications. However, the information regarding the electrical characteristics of 2D materials in aqueous environments for advancing the development of such emerging sensor systems is still unclear. In this report, we have synthesized the bilayer molybdenum disulfide (MoS2) nanomaterials by the chemical vapor deposition method. The layer number of the as-grown MoS2 materials were characterized by using both the Raman spectra and the atomic force microscope (AFM). The selected bilayer MoS2 materials were transferred to a silicon substrate covered with 100 nm-thick SiO2 dielectric layer. The source/drain electrode patterns of the back-gate FETs were defined using an electron beam lithography, followed by the deposition process of the gold thin layer. Importantly, the source/drain electrodes were passivated by the PR layer for reducing the leakage current. After the FET fabrication, the electrical properties of bilayer MoS2 FETs were measured under both the ambient condition and the different concentrations of KCl aqueous electrolyte solutions. From the experimental result of the extracted field-effect mobility, we can evidently find that, when the ionic strength of the KCl electrolyte solution was increased from 0.1 μM to 0.1 M, the values of the ratio of the electron mobility extracted at the aqueous solution to that extracted at the air environment revealed a decreasing trend. The scattering from the ions in the aqueous electrolyte solutions may presumably give rise to the degradation of electron mobility. This report provides information regarding the dependence of the ionic strength on the mobility of atomically thin layered FETs for future sensor applications.

(Keynote) Interface Control for High Performance N-Channel Ge FETs

The demonstration of high electron mobility Ge n-MOSFETs was not an easy task. To overcome such big challenge, three carrier scattering mechanisms in Ge MOS inversion layer such as Coulomb scattering, phonon scattering, and surface roughness scattering were carefully investigated. The first step was to improve the peak electron mobility by reducing the interface states density (Dit ). We succeeded in the reduction of Dit (<1011 eV-1cm-2) at Ge/GeO2 interface by employing the high-pressure O2 (HPO) oxidation [1]. This is quite reasonable thermodynamically [2]. However, there still remained two critical challenges. One was how to suppress the significant degradation of high-Ns electron mobility. The other one was how to keep electron mobility high in thin EOT region [3]. It is generally considered that high-Ns electron mobility is dominated by the interface roughness scattering. Since we demonstrated that Ge(111) was the best surface orientation for electrons to achieve the highest peak electron mobility, we challenged to realize the atomically flat Ge(111) surface by using H2 annealing [4]. Then, MOSFETs on Ge(111) with and without atomically flat surface were fabricated with HPO. N-channel MOSFETs fabricated by HPO on atomically flat Ge(111) exhibited greatly improved high-Ns electron mobility [5]. EOT reduction was also challenging because HPO should naturally form thicker GeO2. This fact was a big hurdle on Ge FET technology. Meanwhile, it was interestingly found that the low-temperature HPO (LT-HPO) reduced the oxidation rate [6]. This fact enabled us to achieve ~2 nm EOT GeO2 on Ge with superior interface and bulk GeO2. Another way to reduce EOT is obviously to replace HPO-GeO2 with other high-k oxides which are appropriate for Ge. We have fortunately found that Y2O3 is very friendly with Ge [7]. Furthermore, in our recent experiments Y2O3-doped GeO2 (YGO) is much better than pure Y2O3 on Ge. Significantly improved electron mobility in n-channel Ge FETs in a wide range of electron density has been achieved, when YGO in addition to H2 annealing has been used for the interfacial layer in gate stacks [8]. Poor electron mobility in n-channel Ge FETs is not true now. We can engineer the Ge interface through understanding of thermodynamics in gate stack formation and of kinetics of both surface planarization and oxidation. Thus, we can safely conclude that Ge is very promising not only for p-channel but also for n-channel FETs.

Radiation resistance of wide-bandgap semiconductor power transistors

Radiation resistance of state-of-the-art commercial wide-bandgap power transistors, 1700 V 4H-SiC power MOSFETs and 200 V GaN HEMTs, to the total ionization dose was investigated. Transistors were irradiated with 4.5 MeV electrons with doses up to 2000 kGy. Electrical characteristics and introduced defects were characterized by current–voltage (I–V), capacitance–voltage (C–V), and deep level transient spectroscopy (DLTS) measurements. Results show that already low doses of 4.5 MeV electrons (>1 kGy) cause a significant decrease in threshold voltage of SiC MOSFETs due to embedding of the positive charge into the gate oxide. On the other hand, other parameters like the ON-state resistance are nearly unchanged up to the dose of 20 kGy. At 200 kGy, the threshold voltage returns back close to its original value, however, the ON-state resistance increases and transconductance is lowered. This effect is caused by radiation defects introduced into the low-doped drift region which decrease electron concentration and mobility. GaN HEMTs exhibit significantly higher radiation resistance. They keep within the datasheet specification up to doses of 2000 kGy. Absence of dielectric layer beneath the gate and high concentration of carriers in the two dimensional electron gas channel are the reasons of higher radiation resistance of GaN HEMTs. Their degradation then occurs at much higher doses due to electron mobility degradation.

Atmospheric Pressure Selective Epitaxial Growth of Heavily in-situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Raising the sources and drains regions of Fully Depleted Silicon-On-Insulator devices is mandatory in order to have enough material for silicidation and obtain low contact resistances. Doping was until the 28 nm technology node carried out using ion implantation. For a variety of reasons, in-situ doping is mandatory in future node transistors, however. We have thus focused on the in-situ phosphorous doping of the Si Raised Sources and Drains (RSDs) used in n-type devices. We have shown in [1] that reduced pressures (e.g. 20 Torr) were harmful in order to obtain at 750°C-800°C high P+ ions concentrations with reasonable Si:P Growth Rates (GR). With SiH2Cl2 + PH3 + HCl, we indeed saturated at [P+] around 1019 cm-3, with a surface poisoning by P atoms that drastically decreased the Si:P GR. Wanting to have a straightforward Si:P co-flow process instead of a more complex Cyclic Deposition/Etch process [2], we have thus studied the in-situ phosphorous doping of Si and Si1-yCy at Atmospheric Pressure (ATM) and in the 700°C – 800°C range. To that end, we have proceeded as follows. In order to gain access to the Si1-yCy:P layer thickness and confirm that layers were indeed single crystalline, we have grown {Si0.8Ge0.2 / Si1-yCy:P} stacks on Si(001) and measured them with X-Ray Reflectivity (which gives access to thickness) and X-Ray Diffraction (crystalline quality assessment), as shown in Figure 1. We have otherwise grown the very same Si1-yCy:P layers on slightly p-type substrates to have pn junctions and determine through four point probe measurements their sheet resistances. Resistivities and thus P+ ions concentrations were extracted by multiplying those by the Si1-yCy:P layer thicknesses (from XRR). We have plotted in Figure 2 the Si:P growth rate and [P+] at 750°C, ATM, this for increasing F(PH3)/F(SiH2Cl2) Mass-Flow Ratios (MFRs). When the SiH2Cl2 mass-flow was fixed, we had a significant increase of the Si:P GR (up to 13.3 nm/min.) and of [P+] (at most 7x1019 cm-3). We have tried to reach higher MFRs by reducing, for the highest PH3 1% in H2 flow deliverable in our tool, the SiH2Cl2 mass-flow. This led to (i) a Si:P growth rate decrease and (ii) to a slight [P+] decrease, instead of the increase hoped for. We have studied in Figure 3 the impact of growth temperature on the Si:P GR and on [P+] for the optimum point of Fig. 2. The activation energy associated with the Si:P growth rate increase with temperature in the 700°C-800°C range was equal to 53 kcal. mol.-1 (e.g. close to the Si-H bond strength), while [P+] was steady at 7x1019 cm-3. We have thus moved over to a PH3 5% in H2 bottle and quantified, at 700°C, ATM, the impact of the PH3 flow on the Si:P growth rate and n-type doping for fixed SiH2Cl2 and HCl mass-flows. We have in Figure 4 a sharp increase, a stabilization then a Si:P GR decrease as the PH3 flow increases, which might be due to surface poisoning. Such a behaviour is associated with a P+ ion concentration that sharply increases then reaches a plateau close to 1020 cm-3. We have used such a co-flow processes to thicken at 725°C, ATM the sources and drains regions of stacked Si nanowires with 50 nm of Si:P. The surface of those RSDs was slightly rough (as for Si:P layers on blanket substrates). Full selectivity versus SiO2 (Buried OXyde) and SiN internal spacers was achieved, however, as illustrated by the SEM images of Figure 5. Finally, we have studied the feasibility of adding SiCH6 to the gaseous mixture in order to have C atoms that would supress B diffusion (p+ pockets to control short channel effects in bulk nMOS transistors) and hopefully inject tensile strain in short Si channels (if the substitutional C content is high enough). Because of the rather high temperature (700°C), we were not able to obtain [Csubst.] above 0.55%, as shown by Figure 6 XRD profiles. We were otherwise faced with a Si1-yCy:P GR that decreased and a layer resistivity that increased as the SiCH6 mass-flow increased (competition between P and C atoms for incorporation in the lattice and electron mobility degradation because of the small size of the C atoms), as shown in Figure 7. The best trade-off was achieved for a F(SiCH6)/F(PH3) MFR close to unity. [1] J.M. Hartmann et al, J. Cryst. Growth 264 (2004) 36 and J. Cryst. Growth 310 (2008) 62. [2] J.M. Hartmann et al., Semicond. Sci. Technol. 28 (2013) 025017 and 025018. Figure 1

Remote Coulomb Scattering in Ge MOSFET with GeOx/Al2O3 Gate Dielectrics

Remote Coulomb scatterings (RCS) on electron mobility degradation are experimentally investigated in Ge based metal-oxide-semiconductor field-effect-transistor (MOSFETs) with GeOx/Al2O3 gate stacks. The mobility is found increased with thicker GeOx (7.8-20.8 Å). The physical origin of this mobility dependence on GeOx thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeOx/Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks are studied. The charge distributions in GeOx/Al2O3 gate stacks are experimentally evaluated. The bulk charges in Al2O3 and GeOx are found negligible. The density of interfacial charge is +3.2×1012 cm-2 at GeOx/Ge interface, and -2.3×1012 cm-2 at Al2O3/GeOx interface. The electric dipole at Al2O3/GeOx interface is found +0.15 V, corresponding to areal charge density of 1.9×1013 cm-2. The origin of this mobility dependence on GeOx thickness is attributed to the RCS due to electric dipole at Al2O3/GeOx interface. And this remote dipole scattering is found play a significant role on mobility degradation. The discovery of this new scattering mechanism indicates that engineering of Al2O3/GeOx interface is key for mobility enhancement and device performance improvement. These results are helpful to understanding and engineering the Ge mobility enhancement. Figure 1

Impact of Sacrificial Cosumption of Substrate By Thermal Oxidation on Electron Mobility of 4H-SiC Mosfets

4H-SiC MOSFETs are extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. A significant degradation of electron mobility in inversion channel has been often reported, however, the dominant factors which deteriorate the channel characteristics have not yet been clarified well. In this study we investigated the effects of thermal oxidation during MOSFET fabrication processes on the quality of substrate surface, from the view point of channel mobility degradation. Lateral n-MOSFETs with various gate length, Lg=80~500 μm, were fabricated on p-type 4H-SiC (0001) wafers with Al-doped epitaxial layers. Source/drain (S/D) regions were formed by P implantation, followed by an activation annealing at 1650°C with a carbon cap. Ni Ohmic contacts for n+ S/D were formed by PMA at 1000°C for 1 min in N2 ambient. Finally Al was deposited and patterned as the gate electrode. Before the gate oxide formation, we intentionally consumed 5~60 nm of SiC substrate by a thermal oxidation followed by a chemical etching of SiO2 in HF solution. The gate oxide was thermally-grown in dry-O2 at 1300°C, followed by a post-oxidation-annealing in O2 at 800°C [1]. The consumed SiC thickness in total, including the gate oxide formation process as the final step, was varied from 9 to 72 nm. As a result, a degradation of field-effect-mobility was clearly observed when the sacrificially-consumed SiC thickness increased. To avoid the additional effects of surface damage due to the high-temperature activation annealing, we also prepared a MOSFET without 1650°C annealing, and successfully observed a further enhancement of channel mobility ~10% by minimizing the consumed SiC thickness during the device fabrication processes. Even though we expected the activation of only a few percentage of implanted P atoms, thanks to the thermal oxidation process at 1300oC for this sample, we could extract the channel mobility after the calibration of the effects of the parasitic resistance from Lg-dependence of channel resistance. These results clearly indicate that the sacrificial consumption of SiC substrate surface results in a monotonic degradation of channel mobility. The mechanism of such deterioration has not been clarified yet, but we believe that a degradation of SiC surface quality, possibly due to an accumulation of Al dopants [2] or interstitial C atoms near the SiC surface during the oxidation processes, would explain such change of MOSFET performance.[1] R. H. Kikuchi and Koji Kita, Appl. Phys. Lett. 105, 032106 (2014).[2] T. Kobayashi et al., Appl. Phys. Express 7, 121301 (2014).

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeOx/Al2O3 gate dielectrics

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal–oxide–semiconductor field-effect-transistors (MOSFETs) with GeOx/Al2O3 gate stacks. It is found that the mobility increases with greater GeOx thickness (7.8–20.8 Å). The physical origin of this mobility dependence on GeOx thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeOx/Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeOx/Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeOx are found to be negligible. The density of the interfacial charge is +3.2 × 1012 cm−2 at the GeOx/Ge interface and −2.3 × 1012 cm−2 at the Al2O3/GeOx interface. The electric dipole at the Al2O3/GeOx interface is found to be +0.15 V, which corresponds to an areal charge density of 1.9 × 1013 cm−2. The origin of this mobility dependence on GeOx thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeOx interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeOx interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.

Influence of Al2O3 layer insertion on the electrical properties of Ga-In-Zn-O thin-film transistors

To investigate the influence of ionic/covalent interface of Al2O3/SiO2 gate insulator on the electrical properties of thin-film transistors (TFTs) with ionic Ga-In-Zn-O (GIZO) semiconducting channel layers, Al2O3 layers of different thickness were introduced between SiO2 and GIZO using plasma-enhanced atomic layer deposition. The GIZO layers were obtained by DC magnetron sputtering using a GIZO target (Ga:In:Zn = 1:1:1 mol. %). The GIZO TFTs with an Al2O3/SiO2 gate insulator exhibited positive threshold voltage (Vth) shift (about 1.1 V), Vth hysteresis suppression (0.23 V), and electron mobility degradation (about 13%) compared with those of a GIZO TFT with SiO2 gate insulator by the influence of ionic/ionic and ionic/covalent interface at Al2O3/GIZO and Al2O3/SiO2, respectively. To clarify the origin of the positive Vth shift, the authors estimated the shifts of flatband voltage (0.4 V) due to the dipole and the fixed charge (−1.1 × 1011/cm2) at Al2O3/SiO2 interface, from capacitance–voltage data for Pt/Al2O3/SiO2/p-Si capacitors. Based on these experimental data, the authors found that the positive Vth shift (1.1 V) could be divided into three components: the dipole (−0.4 V) and fixed charge (0.15 V) at the SiO2/Al2O3 interface, and the fixed charge (1.35 V) at the Al2O3/GIZO interface. Finally, it is noted that heterointerface of SiO2/Al2O3/GIZO stacks is important not only to recognize mechanism of Vth shift but also to design future TFTs with high-k dielectrics and low operating voltage.

(Invited) Effects of Ge Substrate Annealing in H2 on Electron Mobility as well as on Junction Leakage in n-channel Ge MOSFETs

A significant enhancement of electron mobility and understanding of carrier transport physics in Ge MOSFETs have been made thanks to significant reduction of major extrinsic carrier scattering sources such as Dit and surface roughness, in addition to EOT scaling in Ge gate stacks. Since the phonon scattering is the dominant mechanism in Ge bulk, Ge substrate considerations have been out of scope for improving the carrier mobility in Ge MOSFETs. In this talk, however, we report that the peak electron mobility is dependent on how Ge substrates are treated. We found that H2 annealing was quite effective for achieving the atomically flat surface of Ge substrates. In parallel with this effort, we recently found that H2annealing of Ge substrates could improve the peak electron mobility significantly, even though the peak electron mobility on as-received Ge substrates was poor. This fact indicates that there is definitely another origin of electron mobility degradation inside Ge bulk, because the peak electron mobility is not significantly affected by the surface roughness scattering. This fact indicates that electron mobility is not simply understood by considering the scattering mechanisms reported for Si MOSFETs. Here, we report the relationship between electron mobility and oxygen atom concentration in Ge substrate. Furthermore, we discuss effects of oxygen atoms in Ge substrate on reverse-biased n+/p junction leakage current. The oxygen atoms in Ge substrates experimentally reduced the leakage current in n+/p junctions. This result is good news for Ge technology, but it is incompatible with high electron mobility in terms of achieving high performance MOSFETs. Then, we fabricated MOSFETs with selective areal profile of oxygen atoms along the channel and source/drain regions. This method has enabled us to achieve high electron mobility in n-channel Ge MOSFETs together with high Ion /Ioff ratio. Although the junction leakage has been considered to be intrinsically poor in Ge due to a narrower energy band gap, this paper strongly suggests that Ge technology will be further improved for the best with the help of a rich heritage of Si technology.

(Invited) Hetero Interface of Ionic/Covalent Oxides for Nano-Electronics

We investigated the role of hetero interface of ionic high-k and covalent SiO2 on flatband voltage (V fb) and threshold voltage (V th) shifts for CMOS and TFT. The V fb and V th of CMOS and TFT including high-k/SiO2 gate insulator were influenced due to the bottom interface dipole which causes at high-k/SiO2 interface. It is clear from experimental results that the direction and strength of the dipole moment strongly depend on oxygen concentration at high-k/SiO2 interface. We also found that GIZO TFTs with an Al2O3/SiO2 gate insulator exhibited positive V th shift, electron mobility degradation by the fixed charge at Al2O3/GIZO interface and the bottom interface dipole at Al2O3/SiO2 interface. The hetero interface of high-k and SiO2 layers is very important not only for recognizing the mechanism of V fb and V th shifts but also for designing nano-electronic devices with high-k/SiO2 stack structure.

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

In this paper, carrier transport properties in highly scaled (down to 14nm-node) FDSOI CMOS devices are presented from 77K to 300K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100nm devices. The critical lengths were around 50nm and 100nm for NMOS and PMOS devices, respectively.