Degradation In Bipolar Transistors Research Articles

The Influence of Deep-Level Defects With Various Depths in SiO2 on Ionizing Damage

In this article, we analyzed the interaction mechanism between ionization and displacement defects in SiO2 using experimental and simulation techniques. In the experiment, the gate-controlled lateral p-n-p transistors (GLPNPs) were pretreated by He ions irradiation with different energies, which can create additional oxygen vacancy defects (Vo) at various depth ranges in SiO2. The pretreated GLPNPs were irradiated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays to analyze their response to ionization damage. It can be found that the introduction of additional deep Vo in SiO2 weakens the ionization damage of GLPNPs, and this weakening effect is heavily related to the depth of additional deep Vo. In addition, the TCAD simulation tool was used to investigate the mechanism by which the ionization damage is weakened with additional deep Vo depth. The simulation results show that as the additional deep Vo defect approaches the SiO2–Si interface, the additional deep Vo defect enhances the capture of the holes (or release of electrons), resulting in a decrease in hydrogenated Vo ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {Vo}\mathbf {H}_{\mathbf {2}}^{\mathbf {+}}$ </tex-math></inline-formula> ) concentration, which affects the release of protons and ultimately reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{\mathrm {it}}$ </tex-math></inline-formula> . Based on the above mechanism, it would be helpful to accurately evaluate the electrical characteristics degradation of bipolar transistors in complex space environments.

Degradation of bipolar transistors at high doses obtained at elevated temperature applied during gamma-irradiation

The paper presents investigation results of radiation-induced change in current gain of bipolar transistors at elevated temperature applied during gamma-irradiation with high levels of dose. The regularities obtained during irradiation at elevated temperature coincide qualitatively with the data obtained previously during irradiation at low dose rate. Results of simulation confirm the possibility of applying of developed model of radiation induced degradation of bipolar transistor for irradiation at different temperatures.

Impact of nitride passivation layer on ionizing irradiation damage on LPNP bipolar transistors

Bipolar junction transistors (BJTs) are generally employed in spacecraft, due to their current drive capability, linearity and excellent matching characteristics. High-energy particles and cosmic rays in space environment remarkably affect electronic devices, especially in BJTs producing total ionizing dose, displacement damage or single event effect. Among them, ionizing irradiation effects on BJTs dominates. For BJTs, ionization damage can induce the oxide trapped charges in SiO2 layer and interface traps in Si/SiO2, resulting in more recombination base current and the degradation of current gain. Consequently, the accumulation of both oxide charges and interface traps causes an increase in the base current.#br#Passivation layer is also an important factor of the irradiation effects of BJTs. Previous works only studied the degradation of electrical properties of the devices with/without passivation layer induced by irradiation, and did not give an influence mechanisms of passivation layer on the irradiation respond of devices. Therefore, the irradiation damage mechanisms of the BJTs with or without nitride passivation layer are not clear so far.#br#In this paper, the impact of Si3N4 passivation layer on ionizing irradiation damage on lateral PNP bipolar transistors (LPNP) was studied by using 60Co gamma irradiation source. The KEITHLEY 4200-SCS semiconductor parameter analyzer was used to measure the relationship between the electrical properties of LPNP transistors and ionization dose, including the Gummel characteristics, the degradation of current gain, etc. The irradiation defects of the LPNP transistors with/without passivation layer structure were analyzed by the deep level transient spectroscopy (DLTS). The experimental results show that the electrical properties of the LPNP transistors with and without passivation layer exhibit similar characteristics. For all samples, the base current increases with increasing the total dose, while the collector current does not almost change. Compared with the LPNP transistors without Si3N4 passivation layer, the degradation of LPNP transistor with Si3N4 passivation layer is severe.#br#Based on the excess base current as a function of base-emitter voltage for the LPNP transistors with/without nitride passivation layer, the degradation of bipolar transistors with nitride passivation layer is severe under the same irradiation conditions. The DLTS analyses show that compared with the bipolar transistors without nitride passivation layer, the signal peak located at about 300 K is shifted to low temperature for the bipolar transistors with nitride passivation layer. The above results show that the LPNP transistors with nitride passivation could produce a large number of interface states with the energy level is closer to the middle of the forbidden band during the irradiation, which is attributed to a large number of hydrogen presence during the processing of fabricated passivation layer.

Microscopic Hot-Carrier Degradation Modeling of SiGe HBTs Under Stress Conditions Close to the SOA Limit

We present and validate a physics-based model to describe the underlying mechanisms of hot-carrier degradation in bipolar transistors. Our analysis is based on a deterministic solution of the coupled system of Boltzmann transport equations for electrons and holes. The full-band transport model provides the energy distribution functions of the charge carriers interacting with the passivated Si–H bonds along the oxide interface. The simulation results assert the dominant role of hot holes along the emitter–base spacer oxide interface in the long-term degradation of an n-p-n SiGe heterojunction bipolar transistor under low and high-current conditions at the border of the safe-operating area. The interface trap density is calculated by incorporating an energy driven paradigm for the microscopicmechanisms of defect creation into a reaction-limitedmodelwith dispersive reaction rates. These interface traps increase the forward-mode base current via Shockley–Read–Hall recombination and degrade the overall device performance. The Gummel characteristics of a degraded device and time evolution of the excess base current for different stress conditions are verified versus the experimental data obtained for a state-of-the-art toward-terahertz SiGe HBT.

Some features of degradation in bipolar transistors at different test conditions for total ionizing dose effect

The results of studying the degradation in PNP and NPN bipolar transistors at different test conditions for total ionizing dose effect are presented. It is confirmed that the gain change at total ionizing dose testing depends strongly on the electrical conditions. The features of the dose rate impact at the degradation of transistors in a wide range of doses are described.

The temperature dependence of mixed mode degradation in bipolar transistors

The temperature dependence of mixed mode degradation is investigated. It is shown that a standard measure–stress–measure procedure can yield large errors in the extracted activation energy of this degradation mechanism. A new and efficient measurement procedure is presented that allows for an accurate extraction of the temperature dependence. This methodology was applied to our samples and it was found that the mixed mode degradation mechanism exhibits a small negative activation energy.

Modelling and design considerations on CML gates under high-current effects

In this paper, the effect of the transit time degradation of bipolar transistors on the power-delay trade-off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high-speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18(9):1369–1375; Model and Design of Bipolar and MOS Current—Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed-form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power-delay trade-off by considering the effect of the transit time degradation in high-speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil-and-paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20-GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd.

Effect of emitter-base bias during pre-irradiation infrared illumination on the radiation response of bipolar transistors

Enhancement and suppression of radiation-induced current-gain degradation in bipolar transistors has been observed after pre-irradiation infrared (IR) illumination under reverse and forward emitter-base bias, respectively. The effect of the IR illumination decreases during isochronal anneal and almost completely disappears at 100/spl deg/C. A qualitative physical model has been proposed to explain the experimental results. The effect can be caused by an IR-light-induced transition between the neutral and dipole configurations of the precursor defects without changing the net electric charge. Possible applications of the effects are discussed.

Study of radiation effects on bipolar transistors

In this paper it was shown that the irradiation with neutrons and carbon ions leads to gain degradation in bipolar transistors due to generation of defects. The density of these generated defects is independent of the type of irradiation (neutrons or carbon ions). Thus, it is possible to evaluate Δ(1/ β), once the expected Frenkel pair density is known. The dependence of the damage constant on collector current is a power law function, with the exception of the lateral pnp transistors, that shows a higher sensitivity to radiation and a different behaviour. Neutrons give a smaller density of Frenkel pairs (CF) than the two sorts of carbon ions of high energy (CHE) and medium energy (CME). It was found that CME causes a higher concentration of CF. The calculated ratio R=CF/ Φ, where CF is the Frenkel pair density and Φ fluence does not depend on Φ, for a given type of radiation. However, it depends on the incoming particle type. Its smallest calculated value was obtained for neutrons ( R=6.1×10), which increases to 1.25×10 3 for CHE and to 1.1×10 4 for CME.

Process characterisation of hot-carrier-induced β degradation in bipolar transistors for BiCMOS

This paper investigates the effect of various process parameters on the variation in forward current gain lifetime caused by hot carrier generation of BiCMOS bipolar transistors. Statistical process control and statistical designed experiments were used in this evaluation. The device lifetime in reverse bias operation was calculated from the forward current gain. Various process parameters were examined in this work, i.e., the intrinsic base implant dose and energy, selective collector implant dose, collector plug dose, spacer etch ratio, overetch thickness of nitride spacer and emitter poly etch time. It was deduced that high current gain lifetime can be obtained with high base implant doses, high base implant energies, long bulk nitride etch times and short emitter poly etch times.

Dose-rate and irradiation temperature dependence of BJT SPICE model rad-parameters

A method to predict low dose rate degradation of bipolar transistors using high dose-rate, high temperature irradiation is evaluated, based on an analysis of four new rad-parameters that are introduced in the BJT SPICE model. This improved BJT model describes the radiation-induced excess base current with great accuracy. The low-level values of the rad-parameters are good tools for evaluating the proposed high-temperature test method because of their high sensitivity to radiation-induced degradation.

Recent advances in understanding total-dose effects in bipolar transistors

Gain degradation in irradiated bipolar transistors can be a significant problem, particularly in linear integrated circuits. In many bipolar technologies, the degradation is greater for irradiation at low dose rates than it is for typical laboratory dose rates. Ionizing radiation causes the base current in bipolar transistors to increase, due to the presence of net positive charge in the oxides covering sensitive device areas and increases in surface recombination velocity. Understanding the mechanisms responsible for radiation-induced gain degradation in bipolar transistors is important in developing appropriate hardness assurance methods. This paper reviews recent modeling and experimental work, with the emphasis on low-dose-rate effects. A promising hardness assurance method based on irradiation at elevated temperatures is described.

Improved circuit technique to reduce h/sub fe/ degradation in bipolar output drivers

h/sub fe/ degradation in bipolar transistors caused by reverse V/sub be/ stress decreases the reliability of BiCMOS circuits. In this paper, we present an improved circuit technique to limit reverse V/sub be/, and thus significantly increase BiCMOS reliability. The technique also reduces the base-emitter breakdown voltage constraint on BiCMOS technology design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of the temperature dependence of hot-carrier-induced degradation in bipolar transistors for Bi-CMOS

The temperature dependence of emitter-base reverse stress degradation in bipolar transistors for Bi-CMOS circuits was studied. A suitable measure of degradation in the operating temperature range was chosen after careful consideration of the fact that bipolar transistor characteristics are very sensitive to temperature changes. The worst-case temperature conditions within the transistors' operating range were determined. Degradation was found to be worst at around 50/spl deg/C-a result of a tradeoff between thermal recovery from degradation and the effects of bandgap narrowing on bipolar characteristics. The recovery phenomena which had taken place after degradation were also investigated in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Temperature dependence of hot-electron degradation in bipolar transistors

Degradation of the base current and current gain observed in bipolar transistors that were electrically stressed at-75, 175, and 240 degrees C for 1000 h with a constant reverse-bias voltage applied to the emitter-base junctions is discussed. The rate of degradation was found to be temperature-dependent with a larger degradation occurring at the lower temperature. This temperature dependency is studied using an electron energy simulation technique and experimental data on degradation and postdegradation annealing. From the electron energy simulations, the number of hot electrons above a damage threshold energy was seen to increase with increasing ambient temperature at a constant reverse-bias voltage. This increase with temperature occurred because higher stress currents dominated over a reduction in the electron mean free path between collisions at higher temperatures. However, an actual degradation rate reduction at higher temperatures occurs because of simultaneous annealing of the states produced by hot electrons. A model that describes the temperature dependence of degradation and postdegradation annealing is described. >

A model for mechanisms in plastic-encapsulated microelectronic devices during temperature-humidity tests—II

The model is considered in more detail than in Part I of the series, and is verified by results of laboratory tests on humidity absorption and plastication with respect to material analysis and degradation of bipolar transistors with respect to several electric characteristics of temperature-humidity bias. The results confirm the model very well. They allow derivation of methods to increase the reliability of microelectronic devices, and selection of tests and test conditions.

Hot-carrier degradation in bipolar transistors at 300 and 110 K-effect on BiCMOS inverter performance

The degradation of bipolar transistors at 300 and 110 K under DC base-emitter reverse-bias stress is discussed. It is found that, for the same reverse voltage, the reverse current is about three to four times smaller at 100 than at 300 K, but the rate of base current degradation is several times larger. A method for modeling the degradation due to the stress from a periodic signal is proposed. The resulting expression for degradation is compatible with the SPICE bipolar model and has been used to simulate the degradation of a BiCMOS inverter operating at 300 and 110 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Degradation of bipolar transistors under high current stress at 300 K

We have observed the onset of degradation of bipolar transistor characteristics under high current forward stress at room temperature. The observed degradation may be attributed to interface states generated next to the sidewall oxide at the emitter base junction in a self-aligned bipolar transistor. Individual steps in the generation and annealing kinetics may be resolved. The sensitivity of the device to the extrinsic base doping profile is demonstrated and a model based on the generation of hot carriers by Auger recombination and bond breaking by these hot carriers is proposed.

Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design

The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a high V/sub be/, as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the V/sub be/ of the transistors. >