Defects In Stacks Research Articles

Improved Signal Detection Sensitivity for High Resolution Imaging in Scanning Acoustic Tomography

Abstract Scanning acoustic tomography (SAT) is widely used to detect defects such as voids and delamination in electronic devices. In this article, the authors explain how they improved the spatial resolution and detection sensitivity of SAT by switching from a conventional piezoelectric probe to a capacitive micromachined ultrasound transducer (CMUT) and by using pulse compression signal processing. They also present examples showing how the improvement makes it possible to detect very small defects in multilayer stacks and BGA packages whether in through-transmission or reflection imaging mode.

(Invited) Multiscale Modeling of Atom Scale Defects for Electronic Devices Engineering

We present in this paper a multiscale modeling platform that is used to study the effect of atomic level defects on the electrical characteristics of nanoscale devices. This allows identifying ways to engineer material (and defects) and device properties to achieve optimum performance and reliability in logic and memory circuits.Atom scale defects in multilayer thin film material stacks have a profound effect on the electrical performance and reliability of nanoscale electronic devices. These defects include both point defects such as vacancies and interstitial ions as well as extended defects such as grain boundaries, dislocations.We developed a multiscale modeling platform connecting the atomic material properties to the electrical device performance, which allows understanding the optimum material characteristics for different types of logic devices and memory cells. These include logic devices, conventional memories (e.g. DRAM, 3D-NAND) as well as emerging devices (e.g. RRAM, PCM). The simulations allow learning how to scale these technologies through material and process improvement and how to co-optimize materials and devices. I. MULTISCALE MODELING Figure 1 shows the flowchart of the multiscale multiphysics simulation platform along with its main blocks [1]. The ab-initio material properties relevant for the electrical device performances (e.g. bandgap, permittivity, defects energies, defect diffusion barrier ...) are computed using DFT calculations (gray portion). These material properties are then used for the device level simulations (green portion), and the output device electrical characteristics allows calibrating the circuit simulations (yellow portion). The device simulator couples classical and quantum charge transport mechanisms with stress induced material changes (e.g. atomic breakage, creation and diffusion of ions/vacancies), whose occurrence probability is calculated by accounting for the temperature increase and power dissipation associated with the current.The charge transport mechanisms include drift/diffusion in conduction band (CB) or valence band (VB), which is the primary carrier transport mode in semiconductors, and Trap Assisted Tunneling (TAT), which is the dominant mechanism in dielectrics and amorphous semiconductors. Defects with energy levels in the bandgap play a crucial role in the conduction, assisting electron transfer. The charge transport is coupled to the kinetics of atomic level material modifications caused by electrical and thermal stresses encompassing distortion and breakage of bonds, diffusion of vacancies and interstitial ions leading to changes in local fields, stoichiometry and phase changes including ferroelectricity. This allows modeling the reliability of devices to be calculated in addition to static electrical characteristics as well as the device variability.In this presentation, we will show how this multiscale simulation platform can be used to extract defect properties for advanced logic stack as well as to understand the physics of operation of RRAM devices. II. UNDERSTANDING DEFECT IMPACT ON LOGIC STACKS The multiscale approach presented in Section II can be used to characterize and understand the role of the dielectric defects on device electrical characteristics and reliability. Oxide defects are at the bases of the most relevant reliability phenomena in both logic and memory devices, e.g. Random Telegraph Noise (RTN), Bias Temperature Instabilities (BTI), Stress Induced Leakage Currents (SILC) and breakdown (BD). Identifying their nature and their spatial/energy distributions in the dielectric stack is crucial for process optimization and device operation/reliability improvement. The developed simulation framework implements a fast defect spectroscopy (DS) technique based on the modeling and simulation of the charge transport within the dielectric. This technique is applied to identify the defects responsible for I-V, CV. GV in a variety of different stack configurations. III. UNDERSTANDING RRAM OPERATIONS We used this modeling platform proposed to investigate the kinetics of the operation processes of HfO2-based RRAM devices. Forming, set and reset operations are consistently described within the modeling framework described in Section II, accounting for species (i.e. O ions and vacancies) generation, recombination and diffusion.Simulations can reproduce the evolution of the current simulated for a full cycle comprised by forming, reset and set operations. The simulated current exhibits the expected features: an abrupt jump at forming, a gradual reduction in reset, and a lower set voltage compared to forming. The evolution of potential, temperature and generated oxygen vacancies and ions during simulations can be monitored to gain insights on the mechanisms controlling device operations, including the structural changes such as the creation and disruption of the conductive filament, as well as the high temperature reached during forming. IV. REFERENCES [1] GINESTRATM , http://www.mdlsoft.com Fig 1: Schematic flow chart describing the main blocks of multiscale simulation platform. Figure 1

(Invited) Photoemission-Based Characterization of Gate Dielectrics and Stack Interfaces

In the development of Metal-Insulator-Semiconductor (MIS) devices, gate dielectric technologies are of great importance and include major scientific and technological issues to be solved for required device performance and reliability. To gain a better understanding of physics of gate dielectric stacks and insights into interface control, characterization of electronic structures of gate dielectrics and quantification of electronic defects in dielectric stacks are imperative. In this work, we have demonstrated how energy dependent dielectric responses of gate dielectrics are evaluated by photoelectron energy loss spectroscopy (PEELS) [1, 2] and how energy distributions of defect states in wide gap materials and their interfaces are quantified by total photoelectron electron yield spectroscopy (PYS) [3-5]. Determination of Complex Dielectric Function The analyses of core-line photoemission spectra have been extensively conducted to characterize chemical bonding features in materials and heterointerfaces of interest. On the other hand, electron energy loss spectroscopy is an effectively used method for study the excitation spectra of atoms, molecules, and solids. Thus, we have measured and analyzed energy loss signals (ELS) incidental to core-line spectra not only to determine energy bandgap values of dielectrics but also to characterize dielectric functions of dielectrics since, inherently, photoexcited electrons passing through dielectrics can suffer inelastic losses due to electronic excitations such as plasmons and band-to-band transitions. As the first step, we examined a complex dielectric function of 50nm-thick SiO2 grown at 1000 ºC in dry O2 from the ELS analyses of both Si2p3/2 and O1s lines. In each analysis, based on photoelectron take-off angle dependence of ELS, the pure bulk component being proportional to the negative imaginary part of inverse dielectric function was extracted carefully, and then the real part of inverse dielectric function can be calculated by Kramers-Kronig transformation of the extracted bulk component. Almost the same results were obtained from the ELS analyses of both Si2p3/2 and O1s photoelectrons, and are very consistent with the dielectric function calculated from reported optical constants of SiO2 glass [6]. Notice that obtained dielectric function enables us to confirm the validity of the energy band gap value determined simply from the onset energy of ELS. We have extended this PEELS to characterization of dielectric functions of CVD SiO2 formed by reaction between SiH4 and remote O2 plasma, Hf- and Al-silicates prepared by plasma-assisted ALD, and confirmed that spectral broadening and tailing become significant with an increase in structural fluctuation and incorporation of Hf and Al atoms. Quantification of Energy Distribution of Defect States Since photoelectron yield is obtained by counting the total number of photoelectrons emitting from the sample as a function of incident photon energy and normalized by the incident photon flux, the spectrum is related to an integral over the occupied density of states involving photoemission near the sample surface. Changes in photoelectron yield spectrum with wet-chemical thinning of 5.2nm SiO2 formed 500ºC by remote plasma enhanced CVD on n-type GaN(0001) show presence of occupied defects in SiO2, near the interface and in GaN but a relatively large number of defects are located within ~1.5nm from the SiO2/GaN interface. From the 1st derivative of the measured yield spectrum with respect to incident photon energy which leads us to the energy distribution of occupied defect state densities in consideration of density of states of the GaN valence band (VB), we found that occupied states are reduced down to ~1x1011cm-2eV-1 at the energy corresponding to the midgap of GaN near the SiO2/GaN interface with N2 anneal at 800ºC. The defect state density near the conduction band edge, which was crudely estimated in consideration of electron occupation probability based on the Fermi-Dirac distribution, are in good agreements with the result obtained from the capacitance-voltage (C-V) analysis using the Terman method. We also found that, for Hf-silicate with a compositional ratio of Hf/(Si+Hf) = ~75% and a relative dielectric constant of ~16 formed on GaN by plasma-assisted ALD and followed by 800ºC anneal in N2 ambience, a similar energy distribution of defect state density to the 800ºC-annealed SiO2/GaN was obtained in the energy range from ~1eV above the GaN valence band edge toward the conduction band edge.

Contribution of cryoelectron microscopy of vitreous sections to the understanding of biological membrane structure

Using cryoelectron microscopy of vitreous sections, we investigated in situ the ultrastructure of biological membranes, selected from several cell types for their diverse biological functions. Here we describe how to visualize the two membrane leaflets and tightly apposed membranes, lying as close as 1.1 nm apart, by tuning the imaging conditions. We show how defects in membrane stacks may be clues to resolving their structure. Details of membrane proteins are also resolved, as well as protein lattices with correlations between stacked membranes. Imaging the cell in its native hydrated state can now be done in the nanometer resolution range, which should open unique routes for investigating structure-function relationships.

Non-Destructive Evaluation of Deep-Lying Defects in Multilayer Conductors Using HTS SQUID Gradiometer

We examined the ability to detect deep-lying defects in multilayer stacks of aluminum plates using an eddy-current testing technique with HTS planar-type SQUID gradiometers. In addition to a previous gradiometer with a baseline of 1 mm, a new gradiometer with a baseline of 8.5 mm and a larger effective area fabricated by HTS multilayer and ramp-edge junction technologies was used. The frequency and depth dependences of the SQUID signal were compared between the two gradiometers. By employing the longer-baseline gradiometer and an excitation frequency of 35 Hz, a slit-like defect located at about 38 mm in depth could be clearly observed with a signal-to-noise ratio larger than 10.

CONNECTING ELECTRICAL AND STRUCTURAL DIELECTRIC CHARACTERISTICS

An attempt is made to correlate electrical measurement results to specific defects in the dielectric stacks of high-k/metal gate devices. Defect characteristics extracted from electrical data were compared to those obtained by ab initio calculations of the dielectric structures. It is demonstrated that oxygen vacancies in a variety of charge states and configurations in the interfacial SiO2layer of the high-k gate stacks contribute to random telegraph noise signal, time-dependent dielectric breakdown, and the flatband voltage roll-off phenomenon.

(Invited) An Electron-Beam-Induced Current Investigation of Electrical Defects in High-k Gate Stacks

We succeeded in applying electron-beam-induced current (EBIC) technique to visualize the current leakage sites in the MOS devices with HfSiON gate dielectrics. The occurrence of initial leakage sites in fresh devices has been investigated with consideration of the effects of well type, gate size and gate electrode. Stress-induced leakage and breakdown sites were studied by in situ voltage stress and EBIC characterization. Finally, the micro-structure and physical damages at various leakage sites were characterized by TEM. Based on the EBIC and TEM results, the leakage and breakdown mechanisms of HfSiON gate stacks were discussed.

An Electron-Beam-Induced Current Investigation of Electrical Defects in High-k Gate Stacks

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Scanning Transmission Electron Microscopy Studies of Interface Stability and Point Defects in Gate Stacks with High-k Dielectrics

Advanced gate dielectric stacks are comprised of multiple layers of different materials, including high-k gate dielectrics, metal gate electrodes and interfacial layers with sub-nanometer thickness. The composition, point defect chemistry, interface atomic structure and interaction between the layers determine the properties of these gate stacks. This paper reviews recent applications of advanced scanning transmission electron microscopy techniques to determine the atomic structure and defects in advanced gate stacks.

Electrical characterization of high-k gate dielectrics on semiconductors

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) inelastic electron tunneling spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

Novel electrical characterization for advanced CMOS gate dielectrics

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: 1) inelastic electron tunneling spectroscopy (IETS), 2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of an MOSFET, and 3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

Metal Electrode/High-$k$ Dielectric Gate-Stack Technology for Power Management

High- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics have been intensively investigated during the last decade, and their performance as a gate dielectric has been improved to the level of conventional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate dielectric at an equivalent oxide thickness (EOT) ~1 nm. The understanding on metal electrodes and their interaction with the underlying high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric has been expanded, and various CMOS device results with metal electrode/high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectric stacks to future technology generations. A new class of high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric that has a dielectric constant higher than 26 and a barrier height of ~5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.

Bulk and Interfacial Oxygen Defects in HfO2 Gate Dielectric Stacks: A Critical Assessment

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Bulk and Interfacial Oxygen Defects in HfO2 Gate Dielectric Stacks: A Critical Assessment

Oxygen-related point defects can provide fixed charge or act as charge trapping centers in high-k gate stacks and, therefore, their origins and properties are of great interest. In this paper, reported experimental and theoretical results related to oxygen defects in HfO2 gate dielectrics are reviewed critically to assess the relative importance of different defect species in terms of their electrical activity and their contributions to important kinetic processes. In addition to point defects in the "bulk" of HfO2 thin films, defects resulting from differences in oxygen coordination across the internal hafnium oxide/silicon oxide interface are considered.

Fermi level pinning by defects in HfO2-metal gate stacks

Various mechanisms for the Fermi level pinning of p-gate metals on HfO2 are analyzed in detail. It is found that for Fermi energies below the Si valence band, HfO2 can oxidize Si by creating positively charged O vacancies. The band bending due to this vacancy concentration can account for the observed Fermi level pinning of p metals on HfO2.

Electrical Characterization of Advanced Gate Dielectrics for Scaled CMOS Technology

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) Inelastic Electron Tunneling Spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) PASHEI (Pulse Agitated Substrate Hot Electron Injection) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

Nano-characterisation of dielectric breakdown in the various advanced gate stack MOSFETs

Nano-scale physical analysis of breakdown in nano-scale high-κ gate stacks consisting of either polycrystalline-silicon or metal as gate electrode shows that the microstructural defects and damages induced by breakdown in the high-κ gate dielectric are different from that of conventional SiOxNy/poly-Si and Si3N4/poly-Si gate stacks. Chemical analysis using transmission electron microscopy provides useful information about the nature and evolution of the breakdown induced defects in different gate stacks metal-oxide-semiconductor field effect transistors. Together with electrical characterisation, the possible gate leakage conduction mechanism(s) in various dielectric breakdown has been established. This paper reviews the breakdown conduction mechanism(s) and induced defects in high-κ gate stacks in comparison to conventional gate dielectrics. The impacts of the new failure mechanisms on the performance and reliability of various gate stacks are discussed.

Probing Point Defects in Stacks of Ultrathin High-k Metal Oxides on Semiconductors by Electron Spin Resonance: The Si/HfO2 vs the Ge/HfO2 System

Combined electron spin resonance and electrical analysis of (100)Si/HfO2 and (100)Ge/HfO2 interfaces reveals dramatic differences in their interface defect properties. No interfacial Ge dangling bond type defects could be revealed. The observed paramagnetic defects do not correlate with the slow acceptor states dominating the Ge/insulator trap spectrum, and are resistant to passivation. The dangling bond type defects observed, upon hydrogen detachment, at the (100)Si/HfO2 interfaces are the trivalent Si defects common for Si/SiO2 interfaces, Pb0 and Pb1 centers. The density of the Pb0 is higher than in the (100)Si/SiO2 structures and is sensitive to the deposition process. However, the density can be significantly reduced by annealing of the Si/HfO2 structures in O-containing ambient, likely through re-establishing the Si/SiO2 interface. The density of fast interface states closely follows the variations in the Pb0 center density, suggesting it as the dominant contribution to the fast interface states.

Why are clay minerals small?

The most abundant silicates formed under the Earth’s ‘normal’ surface conditions, i.e. clay minerals, are always of small grain size. Under the same conditions, other mineral species such as carbonates, sulphates and oxides may form much bigger crystals. The reason why phyllosilicates formed in soils or in weathered rocks are always of small grain size is not related to the low-temperature-pressure conditions but rather to particular aspects of their crystal structure. Many recently published works describe the order-disorder cation distribution in the tetrahedral and octahedral sheets and the crystal defects in the layer stacks. Related to the Periodic Bond Chains (PBCs) theory, these data suggest that the size and the shape of clay crystallites could depend on the amount of crystal defects in the three axes of symmetry [100], [110] and [110]. The accumulation of crystal defects poisons the crystal growth along one, two or three PBCs. Then, nucleation becomes less energy-consuming than crystal growth and favours the formation of numerous smaller crystals rather than fewer bigger ones.

Probing Point Defects in Stacks of Ultrathin High-k Metal Oxides on Semiconductors by Electron Spin Resonance: The Si/HfO2 vs the Ge/HfO2 System

not Available.