Chip Defects Research Articles

LDDP-Net: A Lightweight Neural Network with Dual Decoding Paths for Defect Segmentation of LED Chips

Chip defect detection is a crucial aspect of the semiconductor production industry, given its significant impact on chip performance. This paper proposes a lightweight neural network with dual decoding paths for LED chip segmentation, named LDDP-Net. Within the LDDP-Net framework, the receptive field of the MobileNetv3 backbone is modified to mitigate information loss. In addition, dual decoding paths consisting of a coarse decoding path and a fine-grained decoding path in parallel are developed. Specifically, the former employs a straightforward upsampling approach, emphasizing macro information. The latter is more detail-oriented, using multiple pooling and convolution techniques to focus on fine-grained information after deconvolution. Moreover, the integration of intermediate-layer features into the upsampling operation enhances boundary segmentation. Experimental results demonstrate that LDDP-Net achieves an mIoU (mean Intersection over Union) of 90.29% on the chip dataset, with parameter numbers and FLOPs (Floating Point Operations) of 2.98 M and 2.24 G, respectively. Comparative analyses with advanced methods reveal varying degrees of improvement, affirming the effectiveness of the proposed method.

A standalone and portable imaging detection system with embedded computing for automated defect inspection of microfluidic devices

The existing methods for defect detection in PDMS microfluidic chips typically involve complex image recognition algorithms or manual inspection and still lack efficiency and reliability. Although some automatic defect detection methods have been proposed in recent years, most of them still rely on external computation systems to deploy. To address these challenges, we propose an independent portable defect detection system with embedded computing for microfluidic devices. This portable system is completely self-contained, integrating an image acquisition module, a control panel module, a power module, and an embedded computing control module to realize chip detection, processing, and result display functions. Experimental results show that the system can effectively detect most of the commonly seen defects in PDMS-based microfluidic chips, proving to be more efficient and reliable than manual inspection. With the control of the embedded system, two detection methods: template matching (based on comparison with standard samples) and automatic defect detection (based on surface defect recognition) were used to identify defects in PDMS-based microfluidic chips. The proposed system can automatically inspect and analyze chips without the need for external laboratory support and can provide a promising solution for future microfluidic chip manufacturing and operation.

In-line imaging and recognition of flip chip fabrication defects by real-time photoacoustic remote sensing system

Microscopic defects in flip chips, originating from manufacturing, significantly affect performance and longevity. Post-fabrication sampling methods ensure product functionality but lack in-line defect monitoring to enhance chip yield and lifespan in real-time. This study introduces a photoacoustic remote sensing (PARS) system for in-line imaging and defect recognition during flip-chip fabrication. We first propose a real-time PARS imaging method based on continuous acquisition combined with parallel processing image reconstruction to achieve real-time imaging during the scanning of flip-chip samples, reducing reconstruction time from an average of approximately 1134 ms to 38 ms. Subsequently, we propose improved YOLOv7 with space-to-depth block (IYOLOv7-SPD), an enhanced deep learning defect recognition method, for accurate in-line recognition and localization of microscopic defects during the PARS real-time imaging process. The experimental results validate the viability of the proposed system for enhancing the lifespan and yield of flip-chip products in chip manufacturing facilities.

Analisis Pengendalian Kualitas Produk Raja Kripik’s Di Kabupaten Sigi

This study aims to determine and analyze the quality control of banana chips in an effort to control the level of banana chip defects and whether the level of defects is within the control limits at Raja Kripik's IKM in Sigi Regency. Data collection methods using interviews, observation, and documentation. The data analysis technique uses the Statistical Quality Control (SQC) method using statistical tools in the form of check sheets and p-charts. The results of this study indicate that the product quality control carried out by Raja Kripik's is within the control limits because the value of the proportion of defects is smaller than the Upper Control Limit (UCL) value.

Analisis Pengendalian Kualitas Menggunakan Metode Statistical Process Control (SPC) Pada Part Lever Comp Throttle Di PT.OMI

PT. OMI is a company that operates in the automotive industry in the Karawang area, the goods it produces are very varied and have quite a lot of customers. To increase customer trust, customer satisfaction is the most important thing, with the aim of knowing the process and quality results of a product by using a p-control chart and knowing the various types of defects that occur in the product. The research uses data collection methods in the form of production data as well as product defect data produced and data processing using p control charts and Minitab software to analyze the causes of types of defects and provide suggestions for companies. The results of production quality control in 2022 samples were obtained CL (Middle limit) is 0.0077%, LCL (Lower limit) is 0.0074% and UCL (Upper limit) is 0.0080%. From the analysis, there are 3 types of defects, namely color defects at 48%, chip defects at 40%, and finally burry defects at 12%. Problems occur due to several causes such as human factors, machines, methods, and materials. To solve these problems, a fishbone diagram was created. Product control at PT OMI is under controlled conditions. Keywords: Control Chart, Defect, Quality

Progress and comparison in nondestructive detection, imaging and recognition technology for defects of wafers, chips and solder joints

ABSTRACT As an essential part of integrated circuit, chip manufacturing has increasingly demanding requirements for quality, cost and others. Some technical limitations and the development direction of miniaturisation and high density have led to defects in the manufacturing process, which affect the performance and life of the chip. Therefore, the detection, identification and classification of defects are very important to improve the chip reliability. Based on the orderly and concise literature research, this paper focuses on a comprehensive review of the main research results in the field of non-contact non-destructive testing imaging methods for chip defects. Firstly, various defects that may occur in the chip design and packaging process are introduced. Then the contact detection methods including manual and probe method are clarified, and the principles, properties and development applications of NDT methods are introduced in detail, also the defect identification methods after imaging are briefly introduced. Moreover, the advantages and limitations of NDT technologies are summarised through comparative studies. Finally, the future development trend of non-destructive testing methods is predicted. This work hopes to provide some reference for the non-destructive testing of chips, which is of great significance for the health testing of chips in the electronics manufacturing industry.

Sub-ppm Methane Detection with Mid-Infrared Slot Waveguides.

Hybrid integration of photonic chips with electronic and micromechanical circuits is projected to bring about miniature, but still highly accurate and reliable, laser spectroscopic sensors for both climate research and industrial applications. However, the sensitivity of chip-scale devices has been limited by immature and lossy photonic waveguides, weak light-analyte interaction, and etalon effects from chip facets and defects. Addressing these challenges, we present a nanophotonic waveguide for methane detection at 3270.4 nm delivering a limit of detection of 0.3 ppm, over 2 orders of magnitude lower than the state-of-the-art of on-chip spectroscopy. We achieved this result with a Si slot waveguide designed to maximize the light-analyte interaction, while special double-tip fork couplers at waveguide facets suppress spurious etalon fringes. We also study and discuss the effect of adsorbed humidity on the performance of mid-infrared waveguides around 3 μm, which has been repeatedly overlooked in previous reports.

ATNet: A Defect Detection Framework for X-ray Images of DIP Chip Lead Bonding.

In order to improve the production quality and qualification rate of chips, X-ray nondestructive imaging technology has been widely used in the detection of chip defects, which represents an important part of the quality inspection of products after packaging. However, the current traditional defect detection algorithm cannot meet the demands of high accuracy, fast speed, and real-time chip defect detection in industrial production. Therefore, this paper proposes a new multi-scale feature fusion module (ATSPPF) based on convolutional neural networks, which can more fully extract semantic information at different scales. In addition, based on this module, we design a deep learning model (ATNet) for detecting lead defects in chips. The experimental results show that at 8.2 giga floating point operations (GFLOPs) and 146 frames per second (FPS), mAP0.5 and mAP0.5-0.95 can achieve an average accuracy of 99.4% and 69.3%, respectively, while the detection speed is faster than the baseline yolov5s by nearly 50%.

A Lightweight Method for Detecting IC Wire Bonding Defects in X-ray Images.

Integrated circuit (IC) X-ray wire bonding image inspections are crucial for ensuring the quality of packaged products. However, detecting defects in IC chips can be challenging due to the slow defect detection speed and the high energy consumption of the available models. In this paper, we propose a new convolutional neural network (CNN)-based framework for detecting wire bonding defects in IC chip images. This framework incorporates a Spatial Convolution Attention (SCA) module to integrate multi-scale features and assign adaptive weights to each feature source. We also designed a lightweight network, called the Light and Mobile Network (LMNet), using the SCA module to enhance the framework's practicality in the industry. The experimental results demonstrate that the LMNet achieves a satisfactory balance between performance and consumption. Specifically, the network achieved a mean average precision (mAP50) of 99.2, with 1.5 giga floating-point operations (GFLOPs) and 108.7 frames per second (FPS), in wire bonding defect detection.

LED Chip Defect Detection Method Based on a Hybrid Algorithm

LED is an extremely important energy-saving lighting products, which has greatly facilitated human life. Meanwhile, it also makes a positive contribution to global carbon neutrality and carbon peaking. Defect detection is a vital part of the production process to control the quality of LED chips. The traditional methods use a microscope for manual visual inspection, which is time-consuming and has inconsistent testing standards, low efficiency, and other deficiencies. To solve these problems, a hybrid algorithm based on geometric computation and a convolutional neural network is proposed for LED chip defect detection. The method takes advantage of the dimensionality reduction of geometric computation to perform coarse detection of defects on preprocessed chip lithography graphs in the form of grid segmentation, which realizes fast coarse screening of large-scale chip samples and reduces postcomputational costs. The convolutional neural network model is used for the secondary fine detection of “suspected defective” chips after geometric coarse screening, and the SPP (spatial pyramid pooling) network model is improved by directly introducing the original feature map into the SPP pooling layer for summation to enhance the global and local feature information of the output feature map. Furthermore, we construct an LED chip image acquisition platform using a high-frequency multimagnification zoom lens, collect training samples of defective chips, and increase the number of samples through image processing techniques. The research introduces the R-CNN, SDD, and YOLO methods to evaluate the superiority of our method in a number of experiments. The experimental results show that our algorithm proposed in this paper has an average precision (AP) of 96.7% for large-scale chip detection with a low defect rate. Compared with other methods, the testing mean average precision (mAP) is 10.39% higher than traditional YOLO v2. The testing mIoU is also 3.63% higher than traditional YOLO v5, the detection speed is also significantly improved, and it has good robustness.

Denoising method of high-frequency ultrasonic detection signals of flip chip based on orthogonal matching pursuit optimized by artificial bee colony

Flip chip technology is one of the most popular packaging technologies. High-frequency ultrasound is often used to detect flip chip defects, but the detection process is subject to noise interference, which affects the accuracy of the detection results. For this problem, we propose an orthogonal matching pursuit (OMP) algorithm optimized by artificial colony (ABC) to denoise the high-frequency ultrasonic detection signal of flip chip. The introduction of ABC effectively reduces the computational complexity of the sparse decomposition of the OMP and changes the space for searching atoms from discrete to continuous, thus reducing the error between the echo signal and the atoms to improve the reconstruction accuracy. In addition, the random search direction of the ABC algorithm is changed to further accelerate the convergence of the algorithm. Finally, the range of atomic parameters is designed and the coefficients are processed to achieve effective denoising using the characteristics of highfrequency pulsed ultrasonic detection. Experiments show that the proposed method can effectively remove the random noise and grain noise from the echo signal and outperforms the matching pursuit (MP) and OMP algorithms.

Small sample classification based on data enhancement and its application in flip chip defection

With the development of chip integration, scanning acoustic microscopy (SAM) technology is widely used in the intelligent inspection of chips. However, only a few SAM images of the chip are acquired for the SAM test, which will lead to a lack of sufficient data for intelligent recognition of the chip defects. To solve this problem, a generative adversarial network with the addition of a residual attention module, RA-GAN, was proposed and applied to a small sample. Firstly, the original generative adversarial network (GAN) was constructed and the residual attention module was added to GAN. Secondly, the part of the generator network was improved for the SAM images of flip chip, which increases the perceptual field and enriches the details of the generated images. Then, the appropriate learning rate was adjusted during the network training phase, which can prevent the overfitting of the model. Finally, an enhanced dataset with improved image quality and quantity was obtained. To evaluate the effectiveness of the reconstructed dataset, deep learning algorithms were used for SAM image classification. The results validate the effectiveness and advancement of combining RA-GAN with traditional image data enhancement, which can be applied for small sample classification in engineering applications.

Molecular Dynamics Simulation of Chip Morphology in Nanogrinding of Monocrystalline Nickel

In this study, the nanogrinding process for single-crystal nickel was investigated using a molecular dynamics simulation. A series of simulations were conducted with different tool radii and grinding methods to explore the effects of chip morphology, friction forces, subsurface damage, and defect evolution on the nanogrinding process. The results demonstrate that the workpiece atoms at the back of the tool were affected by the forward stretching and upward elastic recovery when no chips were produced. Although the machining depth was the smallest, the normal force was the largest, and dislocation entanglement was formed. The small number of defect atoms indicates that the extent of subsurface damage was minimal. Moreover, when spherical chips were produced, a typical columnar defect was generated. The displacement vector of the chip atoms aligned with the machining direction and as the chips were removed by extrusion, the crystal structure of the chip atoms disintegrated, resulting in severe subsurface damage. By contrast, when strip chips were produced, the displacement vector of the chip atoms deviated from the substrate, dislocation blocks were formed at the initial stage of machining, and the rebound-to-depth ratio of the machined surface was the smallest.

The Effect of Purge Flow Rate and Wafer Arrangement on Humidity Invasion Into a Loaded Front Opening Unified Pod (FOUP)

In recent years, the semiconductor industry has continued to advance production techniques and reduce chip feature size. The presence of unwanted moisture during the construction of these features increases the risk of chip defects and reduced yield. During production, smaller integrated circuit (IC) products are more sensitive to the presence of moisture. Therefore, increasing the efficiency of moisture control techniques is very important to decrease the product defect rate. Front opening unified pods (FOUPs) are the plastic enclosure boxes that are designed to provide a cleaner environment for semiconductor wafers during manufacturing and storage. Clean dry air (CDA) or nitrogen (N₂) can purge moist air out from the FOUP. For the first time, in this study the effect of purge flow rate on the moisture removal efficiency of a loaded FOUP was examined accurately via smoke flow visualization, particle image velocimetry (PIV) and relative humidity (RH) measurement. Moreover, two different wafer arrangements of top-empty and bottom-empty FOUP were investigated. The findings show the bottom-empty FOUP arrangement results in higher purge performance compared to the top-empty FOUP arrangement. Four purge flow rates of 130, 200, 300 and 400 LPM were examined. The findings also show that when the purge flow rate was set to 200 LPM, the lowest level of relative humidity was measured inside the FOUP. Therefore, the purge flow rate of 200 LPM and the bottom- empty FOUP arrangement can minimize the humidity invasion into a loaded FOUP. The findings from this study can be beneficial to the industry to optimize the purge flow rate and to define the most efficient arrangement of the wafers inside the FOUP during manufacturing and storage. This can increase the product quality and reduce energy consumption by decreasing product defects and increasing yield.

Small object detection method with shallow feature fusion network for chip surface defect detection

The development of intelligent manufacturing often focuses on production flexibility, customization and quality control, which are crucial for chip manufacturing. Specifically, defect detection and classification are important for manufacturing processes in the semiconductor and electronics industries. The intelligent detection methods of chip defects are still challenge and have always been a particular concern of chip processing manufactures in an automated industrial production line. YOLOv4 method has been widely used for object detection due to its accuracy and speed. However, there are still difficulties and challenges in the detection for small targets, especially defects on chip surface. This study proposed a small object detection method based on YOLOv4 for small object in order to improve the performance of detection. It includes expanding feature fusion of shallow features; using k-means++ clustering to optimize the number and size of anchor box; and removing redundant YOLO head network branches to increase detection efficiency. The results of experiments reflect that SO-YOLO is superior to the original YOLOv4, YOLOv5s, and YOLOv5l models in terms of the number of parameters, classification and detection accuracy.

A Deep Convolutional Generative Adversarial Network Based Unsupervised Method for Inspecting Ic Chip Defects

A Deep Convolutional Generative Adversarial Network Based Unsupervised Method for Inspecting Ic Chip Defects

A Deep Convolutional Generative Adversarial Network Based Unsupervised Method for Inspecting Ic Chip Defects

A Deep Convolutional Generative Adversarial Network Based Unsupervised Method for Inspecting Ic Chip Defects

ANALISIS KONTROL KUALITAS DENGAN METODE SIX SIGMA UNTUK MENCEGAH PRODUK CACAT PADA KERIPIK PISANG

UKM 99 is a company that produces snacks made from nature, after the COVID-19 pandemic in the industrial world, both in services and manufacturing, there have been many changes. Each company develops each other to dominate the market. In terms of customer satisfaction and the quality of the products produced, the company makes improvements to the quality that has been applied. In UKM 99 which the author studied there were many problems with the quality of production, namely product defects, including: charred, thickness of chips, frying errors. The purpose of this study was to determine the cause of product defects in banana chips produced by UKM 99. Six sigma is a method of quality control and improvement. By using the six sigma method, it can be seen how the quality of banana chips produced by UKM 99. The six sigma approach in this study can be said that there are three causes of the highest product failure, namely: banana chips by 35.85%, thickness and frying techniques each percentage namely 33.96% and 30.19%

A dual mode self-test for a stand alone AES core.

Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform's reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.

Application of the six sigma DMAIC in quality control of potato chips to reduce production defects

To produce competitive products, Small Medium Enterprises (SMEs), one of which is Agronas as a potato chip producer in Batu City, must continue to improve the quality of their products by minimizing production defects. Quality defects on potato chips occurred in color, crispness, wholeness, and size consistency indicators. This study aimed to identify and analyze the factors causing defects in potato chips and to design alternative improvement strategies. The research method used is Six Sigma Define, Measure, Analyze, Improve dan Control (DMAIC), with a sample size of 15 packs for each variable. The results showed that the main priority of the defined stage for quality improvement was crispness and size consistency with a Critical To Quality (CTQ) value of 80.2%. In the measuring stage, based on the process capability value, the final result is 82.3% which has a value above the industry standard in Indonesia of 69.2%. The result of the analysis of the DPMO value of 177,425 is equivalent to 2.43 sigma. The priority of improvement is the two highest defect levels of crispness and size consistency. Factors causing defects in potato chip crispness include limited manpower, lack of supervision and training, different levels of quality, manual packaging, and less than optimal frying. Alternative improvement strategies are labor controlling from the manager, providing training and process SOPs, supervising the selection of raw materials, and checking packaging equipment regularly. Factors causing defects in potato chips’ size consistency include limited manpower, lack of supervision and training, and the absence of a chip rating machine. Alternative improvements include training and process SOPs, supervision in grading chips, and procurement of grading machines.