Deep Trench Technology Research Articles

A Study on the Charge Balance Characteristics of Super Junction MOSFET with Deep-Trench Technology

A Study on the Charge Balance Characteristics of Super Junction MOSFET with Deep-Trench Technology

Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM

We report experimental characterization and modeling of direct and trap-assisted tunneling (TAT) in high-K metal gate (HKMG)-based access transistor and deep trench (DT) capacitor constituting a 32 nm embedded dynamic random access memory (eDRAM) device. This is the first eDRAM technology that has successfully integrated HKMG-based access transistor and DT technology. The experimental results are compared with direct and TAT models implemented in a finite element-based device simulator. While in HKMG-based nFET both TAT, and direct tunneling are present, in the DT capacitor TAT is dominant due to higher interface and bulk traps. We demonstrate, through ab initio simulations, that the bulk and interface traps arise due to oxygen vacancies (Ov) in the bulk HfO2, and SiO2/HfO2 interface and quantitatively compare direct and TAT currents with experimental results.

Reverse-Conducting IGBT Using MEMS Technology on the Wafer Back Side

In this paper, we present a 600-V reverse conducting insulated gate bipolar transistor (RC-IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC-IGBT uses the deep reactive-ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC-IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.

A Robust 3-D Structure for Superjunction VDMOS Under Unclamped Inductive Switching Condition

A novel 3-D structure for Superjunction (SJ) VDMOS which results in high avalanche energy (EAS) under unclamped inductive switching condition without degrading the ON-state current capability is reported in this paper. The proposed structure fabricated in deep trench technology has segmented n+ source region and strip gate. The novel structure can suppress the hole current path beneath the n+ source region under avalanche breakdown condition because of the p+ region which is located between the segmented n+ source regions. In order to verify the mechanism, numerous 3-D simulations are performed using Sentaurus TCAD. As a result, the measurement shows that the robust deep trench SJ-VDMOS improved the EAS by more than six times compared with the conventional structure.

A Novel Coplanar-Waveguide Band-Pass Filter Utilizing the Inductor–Capacitor Structure in 0.18 µm Complementary Metal–Oxide–Semiconductor Technology for Millimeter-Wave Applications

A low-insertion-loss V-band complementary metal–oxide–semiconductor (CMOS) band-pass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) can be tuned individually by adjusting the value of the series capacitor (Cs) and the size of the built-in inductor–capacitor (LC) resonator, respectively. The folded short-stub technique is used to reduce the chip size of the filter. To reduce the silicon substrate loss, the CMOS-process-compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, the filter achieves insertion-loss (1/S21) lower than 3 dB over the frequency range of 46.5–85.5 GHz. The minimum insertion-loss is -1.8 dB at 60 GHz.

Electronic packaging of the IBM System z196 enterprise-class server processor cage

In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Micromachinned monopole antenna by CMOS‐Compatible deep trench technology

AbstractA monopole antenna fabricated by standard 0.18 μm CMOS technology is post‐IC processed by CMOS compatible inductively coupled plasma etching, which can remove the silicon substrate selectively under the metal strips. After substrate release, the resonance of the monopole antenna reveals owing to elimination of the energy confinement from the high‐dielectric media. Experimental results show an improvement of input return loss (S11) from −9 to –14.3 dB by such substrate release technique. The power transfer ratio also increases from 0.87 to 0.96 for better radiation efficiency. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2971–2973, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26403

A 4.9-dB NF 53.5- to 62-GHz micromachined CMOS wideband LNA with small group-delay-variation

A 53.5- to 62-GHz wideband low-noise amplifier (LNA) with excellent phase linearity property using standard 0.13 μm CMOS technology is reported.To achieve sufficient gain, the LNA is composed of six cascade common-source stages. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3 to −19.5 dB, output return loss (S22) of −13.8 to −27.8 dB, forward gain (S21) of 8.1 to 11.1 dB, and reverse isolation (S12) of −49.9 to −60.2 dB over the 53.5- to 62-GHz-band. The minimum NF (NFmin) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S21 (S21-max) of 13.2 dB (at 58 GHz), 2.1 dB higher than that (11.1 dB) of the STD LNA (at 58.5 GHz). In addition, the ICP LNA achieved NFmin of 4.9 dB (at 61 GHz), 0.5 dB lower than that (5.4 dB) of the STD LNA (at 62 GHz). These results demonstrate the proposed LNA architecture in conjunction with the backside ICP deep-trench technology is very promising for high-performance 60-GHz-band RFIC applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2427–2432, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25500

1.8‐dB insertion‐loss planar UWB CMOS bandpass filter with suspended inductors

AbstractThis article demonstrates a low insertion‐loss ultra‐wideband (UWB) CMOS bandpass filter (BP‐filter). Low insertion‐loss was achieved by adopting microstrip‐line (MSL) with optimized ground‐plane pattern as the needed small‐inductance inductors. In addition, to reduce the substrate loss of the large‐inductance spiral inductors, the underneath silicon was removed with the CMOS‐compatible backside inductively coupled plasma deep trench technology. This filter achieved insertion‐loss (1/S21) lower than 3 dB over the frequency range of 4.3–11.2 GHz, stop‐band rejection better than 25 dB over the frequency range of 0–2.3 and 17.4–36.8 GHz, and input return loss (S11) better than −10 dB over the frequency range of 3.1–15.8 GHz. The minimum insertion‐loss was 1.8 dB at 7 GHz. To our knowledge, this is the best result ever reported for a CMOS BP‐filter with operation frequencies higher than 3 GHz. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2946–2948, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24806

A micromachined SiGe HBT ultra‐wideband low‐noise amplifier by BiCMOS compatible ICP deep‐trench technology

AbstractIn this article, we demonstrate that the power gain (S21) and noise figure (NF) performances of a SiGe HBT Ultra‐Wideband Low‐Noise Amplifier (UWB LNA) can be remarkably improved by removing the silicon underneath the UWB LNA with BiCMOS‐process compatible backside inductively‐coupled‐plasma (ICP) deep trench technology. The results show that increases of 1.9 dB (from 11.2 dB to 13.1 dB) and 4.2 dB (from 7.7 dB to 11.9 dB) in S21, and decreases of 0.59 dB (from 5.08 dB to 4.49 dB) and 0.74 dB (from 6.2 dB to 5.46 dB) in NF were achieved at 10 GHz and 13 GHz, respectively, for the SiGe HBT UWB LNA after the backside ICP dry etching. The excellent performances of the SiGe HBT UWB LNA with suspended inductors suggest that it is very suitable for UWB system applications. Besides, the BiCMOS‐process compatible backside ICP etching technique is very promising for BiCMOS integrated circuit (IC) applications. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2598–2601, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24691

Micromachined V-band CMOS bandpass filter with 2 dB insertion loss

A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) can be tuned by the series-feedback capacitor Cs and the parallel-feedback capacitor Cp, respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion loss (1/S21) lower than 3 dB over the frequency range 52.5–76.8 GHz. The minimum insertion loss was 2 dB at 63.5 GHz, the best results reported for a V-band CMOS bandpass filter in the literature.

Micromachined 50 GHz/60 GHz Phi filters by CMOS compatible ICP deep trench technology

AbstractMicromachined 50 and 60 GHz millimeter‐wave filters were implemented by using a 0.18 μm CMOS technology. The CMOS‐compatible inductively coupled‐plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filters completely, and so the substrate loss of the filters can be significantly reduced. The results show that 3.2, 2.6, and 2.1 dB improvements in S11, S21, and GAmax, respectively, are achieved for the 60 GHz filter after the backside ICP etching. Besides, for the 50 GHz filter, a 295.8% (from 9.6 to 38) improvement in Q‐factor of its inductors is achieved. These results show that the backside ICP etching is effective to reduce the substrate loss and parasitic capacitance in the millimeter‐wave frequency bands, and hence is very promising for millimeter‐wave CMOS RFIC applications. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3142–3146, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23915

Micromachined CMOS E‐band bandpass coplanar filters

AbstractIn this work, E‐band CMOS coplanar filters, whose initial design is made according to quasi‐ TEM‐approximation‐based analytical models, are implemented. To study the substrate effects, the CMOS‐compatible inductively coupled‐plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter completely. For the filter with top metal thickness of 0.93 μm after the backside ICP etching, the results show that the input matching bandwidth, i.e. S11 below −10 dB, moves from lower 39.8–81.4 GHz‐band to higher 55.9–94.1 GHz‐band, and the 3‐dB bandwidth of S21 moves from lower 43.5–76.3 GHz‐band to higher 54.5–93.3 GHz‐band. In addition, a 4.67 dB improvement [from −8.86 dB (at 58.5 GHz) to −4.19 dB (at 74.5 GHz)] in peak S21 was achieved. These results show that for the design of passive coplanar devices in the E‐band, the quasi‐TEM‐ approximation‐based analytical models can be used and the backside ICP etching is effective to reduce the substrate loss and parasitic capacitance. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3123–3125, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23873

A Miniature Micro-Machined Millimeter-Wave Bandpass Filter By Complementary Metal–Oxide–Semiconductor Compatible Inductively-Coupled-Plasma Deep-Trench Technology

In this paper, we demonstrate that miniature millimeter-wave band-pass filter can be obtained by replacing the traditional coplanar waveguide structures with the miniature lumped-spiral inductors and metal–insulator–metal (MIM) capacitors. To study the silicon substrate effects on the performances of the miniature spiral inductor and band-pass filter, complementary metal–oxide–semiconductor (CMOS)-process-compatible backside inductively-coupled-plasma (ICP) deep-trench technology was used to selectively remove the silicon underneath them. The results show that a 70.9% (from 5.8 to 9.91) and a 298.7% (from 2.33 to 9.29) increase in Q-factor were achieved at 40 and 60 GHz, respectively, for a 251.7 pH miniature spiral inductor after the backside ICP dry etching. In addition, a 0.9 dB (from -5.4 to -4.6 dB) improvement in peak insertion loss (S21) was achieved for a miniature band-pass filter with 3-dB bandwidth of 47.7 GHz (18.4–66.1 GHz) after the backside ICP dry etching. The chip area of the miniature band-pass filter was only 206×106 µm2 excluding the test pads.

Ultralow-Loss and Broadband Micromachined Transmission Line Inductors for 30–60 GHz CMOS RFIC Applications

In this paper, for the first time, we demonstrate that ultralow-loss and broadband transmission line (TL) inductors can be obtained by using the CMOS-process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the TL inductors. The results show that a 112.8% (from 14.37 to 30.58) and a 201.1% (from 6.33 to 19.06) increase in Q-factor, a 9.7% (from 0.91 to 0.998) and a 28.3% (from 0.778 to 0.998) increase in maximum available power gain G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> , and a 0.404-dB (from 0.412 to 7.6times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> dB) and a 1.082-dB (from 1.09 to 8.4times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> dB) reduction in minimum noise figure NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> were achieved at 30 and 60 GHz, respectively, for a 162.2 pH TL inductor after the backside ICP dry etching. The state-of-the-art performances of the on-chip TL inductors-on-air suggest that they are very suitable for application to realize ultralow-noise 30-60-GHz CMOS radio-frequency integrated circuit. In addition, the CMOS-process compatible backside ICP etching technique is very promising for system-on-a-chip applications.

A High-Performance Micromachined RF Monolithic Transformer With Optimized Pattern Ground Shields (OPGS) for UWB RFIC Applications

In this brief, we demonstrate that high-quality-factor and low-power-loss transformers can be obtained if the optimized pattern ground shields (OPGS) of polysilicon is adopted and the CMOS process-compatible backside inductively coupled-plasma (ICP) deep-trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS, which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 69.3% and a 253.6% increase in quality factor, a 10.5% and a 14% increase in magnetic-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Im</sub> ), a 17.2% and a 51.1% increase in maximum available power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> ), and a 0.682- and a 1.79-dB reduction in minimum noise factor (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) were achieved at 5 and 8 GHz, respectively, for a bifilar transformer with an overall dimension of 230times215 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>

Characterization and Modeling of Pattern Ground Shield and Silicon-Substrate Effects on Radio-Frequency Monolithic Bifilar Transformers for Ultra-Wide Band Radio-Frequency Integrated Circuit Applications

In this paper, an analysis of the effects of pattern-ground-shield (PGS) and silicon-substrate on the performances of RF monolithic bifilar transformers are demonstrated. It was found that high-quality-factor and low-power-loss transformers can be obtained if the optimized PGS (OPGS) of polysilicon is adopted and the complementary metal–oxide–semiconductor (CMOS)-process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS (CPGS), which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 253.6% (from 3.79 to 13.4) increase in Q-factor, a 14% (from 0.7 to 0.798) increase in magnetic-coupling factor (kIm), a 51.1% (from 0.55 to 0.831) increase in maximum available power gain (GAmax), and a 1.79 dB (from 2.597 to 0.807) reduction in minimum noise factor (NFmin) were achieved at 8 GHz for a bifilar transformer with an overall dimension of 230×215 µm2.

Micromachined 22 GHz PI filter by CMOS compatible ICP deep trench technology

A K-band second-order bandpass filter with planar inductive pi-network using CMOS technology is demonstrated for the first time. To reduce the substrate loss of the filter, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, a 55.5-92.2% improvement in quality factor is achieved for the inductors in the filter. In addition, a 1.1 dB improvement in maximum available power gain (G Amax ) in K-band is achieved for the filter after the ICP etching. These results show that the micromachined pi (PI) filter is very promising for microwave/millimetre-wave RFIC applications

An Analysis of Perfect-Magnetic-Coupling Ultra-Low-Loss Micromachined SMIS RF Transformers for RFIC Applications

Selective removal of the silicon underneath a set of single-turn multilayer interlaced stacked (SMIS) radio-frequency (RF) transformers with nearly perfect magnetic-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IM</sub> ~1) and high resistive-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Re</sub> ) is demonstrated. This process is based on the inductively coupled-plasma (ICP) deep trench technology. Improvement of 20.6 and 15.7 dB in isolation (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) were achieved at 5.2 and 8 GHz, respectively, for a dummy open device after the backside ICP etching. Q-factor increases of 102% (from 4.96 to 10.03) and 23.2% (from 2.24 to 2.76), G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> increases of 11.8% (from 0.76 to 0.85) and 4.5% (from 0.88 to 0.92), and NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> decreases of 0.49 dB (from 1.22 to 0.73 dB) and 0.19 dB (from 0.55 to 0.36 dB) were achieved at 5.2 and 8 GHz, respectively, for an SMIS transformer with an overall dimension of 170times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> after the backside ICP etching. The G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.85 and 0.92 are both state-of-the-art results among all reported on-chip transformers. Furthermore, the reasons why the SMIS transformer exhibits better performances than the traditional bifilar and the traditional stacked transformer are explained. These results show that the micromachined SMIS transformers are very promising for RF integrated circuit applications

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> ), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> ) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> after the backside ICP etching. The values of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications