Abstract
A low-insertion-loss V-band complementary metal–oxide–semiconductor (CMOS) band-pass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) can be tuned individually by adjusting the value of the series capacitor (Cs) and the size of the built-in inductor–capacitor (LC) resonator, respectively. The folded short-stub technique is used to reduce the chip size of the filter. To reduce the silicon substrate loss, the CMOS-process-compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, the filter achieves insertion-loss (1/S21) lower than 3 dB over the frequency range of 46.5–85.5 GHz. The minimum insertion-loss is -1.8 dB at 60 GHz.
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