Abstract
A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following feature: the low-frequency transmission-zero (ω z1 ) and the high-frequency transmission-zero (ω z2 ) can be tuned by the series-feedback capacitor C s and the parallel-feedback capacitor C p , respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupledplasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion-loss (1/S 21 ) lower than 3 dB over the frequency range of 52.5–76.8 GHz. The minimum insertion-loss was 2 dB at 63.5 GHz. To the authors' knowledge, this is the best result ever reported for a V-band CMOS bandpass filter in the literature.
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