Abstract
A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) can be tuned by the series-feedback capacitor Cs and the parallel-feedback capacitor Cp, respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion loss (1/S21) lower than 3 dB over the frequency range 52.5–76.8 GHz. The minimum insertion loss was 2 dB at 63.5 GHz, the best results reported for a V-band CMOS bandpass filter in the literature.
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