Deep Sub-micron Technology Nodes Research Articles

Variable Length and Temperature-Dependent Analysis of MLGNR at Nano-Scale Regime

In this paper, a thermally aware equivalent single conductor is proposed, along with analytical modeling to evaluate the parasitic parameters of multilayer graphene nanoribbon (MLGNR) as interconnect, and its performance is analyzed in terms of delay and power delay product (PDP) for 32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm technology nodes at variable global interconnect lengths (500–2000[Formula: see text]m). It was examined that with rising temperature, there is a strident decrease in the mean free path (MFP) of GNR interconnect, which further influences its own resistance at global length (2000[Formula: see text][Formula: see text]m) for all three technology nodes. The simulation tool Simulation Program with Integrated Circuit Emphasis (SPICE) is used to estimate and compare MLGNR performance in terms of signal delay and PDP for three different technology nodes. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (500–2000[Formula: see text][Formula: see text]m) over a temperature range of 200–500[Formula: see text]K for deep submicron technology nodes (16[Formula: see text]nm, 22[Formula: see text]nm and 32[Formula: see text]nm). A similar investigation was performed on the copper interconnect, and it was discovered that the MLGNR performs better in terms of delay and PDP at global levels with a temperature range of 200–500[Formula: see text]K for nano-scaled technology nodes (32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm).

Radiation-tolerant all-digital clock generators for HEP applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

This work presents a novel low-leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep submicron technology nodes, it includes static noise margin monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of the first failure. As proof of concept, a macro of 1 Mb is fabricated in 22-nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.

An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model

Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.

Mixed CNT bundles as VLSI interconnects for nanoscale technology nodes

The continuous miniaturization of very large-scale integration devices impacts the performance of integrated circuits. The performance of existing interconnect materials such as copper has become saturated beyond the deep-submicron technology node, motivating the search for new interconnect materials that could be efficiently employed in such circuits. In this study, a temperature-dependent analysis is performed to determine the propagation delay, power dissipation, and power–delay product of copper, single-walled carbon nanotubes (SWCNTs), multiwalled carbon nanotubes (MWCNTs), double-walled carbon nanotubes (DWCNTs), and mixed (multi- and double-wall) carbon nanotube bundle (MDCB) structures. The performance of these bundled structures is examined with the help of a complementary metal–oxide–semiconductor driver interconnect load system at various temperatures (200–500 K) and technology nodes (22 and 16 nm). The proposed novel mixed structure with MWCNTs at the periphery and DWCNTs in the center is interesting due to the combination of the excellent conducting properties of DWCNTs and the reduction of the net capacitive coupling due to the MWCNTs. Indeed, it is observed that this MDCB interconnect structure can outperform not only copper interconnects but also the SWCNT, MWCNT, and DWCNT structures. Such mixed structures could be used as interconnect materials in high-speed integrated circuits at future nanotechnology nodes.

A VDTA-based robust electronically tunable memristor emulator circuit

In this paper, a fully-integrated tunable grounded memristor emulator circuit based on voltage differencing transconductance amplifier (VDTA) has been proposed. The proposed memristor emulator circuit utilizes two VDTA active building blocks, two grounded resistors, a grounded capacitor and a four-quadrant analog multiplier. The working concept along with the detailed derivation of the mathematical model of the circuit has been discussed numerically and analytically to validate the operation of the proposed emulator. The operations of the proposed emulator circuit, as governed by the established model, have been verified by performing simulations in Cadence Virtuoso at 45 nm technology node. Robustness analyses performed, reveal significant process-variation tolerance at deep sub-micron technology node.

Thermally Aware Modeling and Performance Analysis of MLGNR as On-Chip VLSI Interconnect Material

In this study, a thermally aware electrical equivalent single conductor along with an analytical model to evaluate the parasitic parameters of multilayer graphene nanoribbon (MLGNR) as an on-chip very-large-scale integration interconnect is proposed and its performance is analyzed in terms of delay, power dissipation, and power delay product (PDP) with variable temperatures ranging from 200 K to 500 K for 32 nm, 22 nm, and 16 nm technology nodes. It was observed that with a rise in the temperature, there is a sharp decrease in the mean free path of the GNR interconnect, which further dominates its own resistance at variable global lengths (500–2000 μm) for all three technology nodes. The Simulation Program with Integrated Circuit Emphasis (SPICE) simulation tool is used to estimate and compare the performance of MLGNR in terms of signal delay, power dissipation, and PDP for three different technology nodes. It is revealed from the results that the propagation delay and PDP increase with increasing temperature. A similar analysis was also done for the copper interconnect and it was found that the MLGNR gives better performance in terms of delay, power dissipation, and PDP, at long interconnects (2000 μm) over a temperature range of 200–500 K for deep submicron technology nodes (32 nm, 22 nm, and 16 nm).

Comparative Analysis of Mixed CNTs and MWCNTs as VLSI Interconnects for Deep Sub-micron Technology Nodes

This research paper presents a performance analysis of the mixed carbon nanotube (CNT) as an interconnect for very large-scale integration (VLSI) circuits at deep sub-micron (DSM) technology nodes. The mixed CNT interconnect is a combination of multiwall CNTs (MWCNTs) and single-walled CNTs (SWCNTs). Using hierarchical modeling, a multiconductor circuit model is proposed for the mixed CNT bundle at global-level interconnect lengths. Due to the insertion of SWCNTs in a MWCNT interconnect, the overall density of the conducting tubes in the proposed mixed CNT interconnect structure increases, thereby decreasing the overall resistance and inductance of the mixed CNTs. The performance of the proposed mixed CNT interconnect is estimated in terms of delay and power delay product (PDP) for different technology nodes (32 nm, 22 nm, and 16 nm) at different interconnect lengths. For comparative analysis, a similar analysis is performed using MWCNT bundle interconnects. The comparative results show that there is reduction in the overall propagation delay and PDP for the proposed mixed CNTs compared to MWCNTs as the interconnect material for DSM technology nodes at global-level interconnect lengths.

A Layout-Based Rad-Hard DICE Flip-Flop Design

The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET = 37 MeV·cm2/mg compared to the traditional DICE structure.

Workload- and process-variation aware voltage/frequency tuning for energy efficient performance sustainability of NTC manycores

The power-wall raised by the stagnation of supply voltage in deep-submicron technology nodes, is now the major scaling barrier for moving towards the manycore era. At the same time, the adoption of manycore architectures is considered to be crucial for satisfying the increasing computational power demands and throughput requirements imposed by the explosion in software complexity and volume. The rise of the so-called Dark Silicon, caused by the power budget violations that allow only a small portion of the available computational resources to be simultaneously exploited, points to the direction of energy efficient platforms. Near-Threshold voltage Computing (NTC) has emerged as a promising approach to overcome the manycore power-wall, at the expense of higher sensitivity to process variation and reduced performance which can be compensated with massive parallelization. Given that several application domains operate over specific performance constraints, the performance sustainability is considered a major issue for the wide adoption of NTC. In this work, assuming a feasible, low overhead Power Delivery Network (PDN) for NTC, we investigate how performance guarantees can be ensured when moving towards NTC manycores through a variability-aware voltage and frequency allocation methodology, showing that performance can be efficiently sustained at the NT region while reducing energy dramatically. Additionally, we propose an algorithm for balancing throughput under process (and workload) variation that sustains performance while providing significant energy savings.

Comparative Analysis of On-Chip Optical and Copper VLSI Interconnects for Deep Sub-Micron Technology Nodes

Comparative Analysis of On-Chip Optical and Copper VLSI Interconnects for Deep Sub-Micron Technology Nodes

BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation using LM algorithm on 0.18 micron Technology node

The industry standard BSIM3v3 and BSIM4.0 is replaced by new BSIM6.0 compact MOSFET model for deep submicron technology node. The BSIM6.0 will be next generation and defacto industry standard model for bulk MOSFET. It has inherited the concept of charge based continous model from the European standard EKV model which is also very popular among academics and analog designer community. BSIM6 is a combined effort by BSIM and EKV modeling group based on charge based continous equations. Although there are limitation on certain aspects of EKV model but it still offer its own benefits to have first cut design methodology because of its much simplified analytical equations. The inversion coefficient(IC) has been found extensive acceptance in designer community as it offers more design elegancy in EKV then more complicated BSIM model. This paper discuss first step in analog design process by extracted core EKV2.6 intrinsic model parameters from industry standard BSIM3v3 model on 0.18 micron technology node. The 0.18 micron technology is chosen as it is still more common technology node in analog circuits design. The model parameters are extracted for different bins and optimisation is done using nonlinear optimisation LM algorithm. The optimised EKV2.6 parameters are validated on different I-V's, intrinsic voltage gain and Early voltage circuit parameters.

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

In a typical GPGPU, the on-chip storage is critical to the massive parallelism and is desired to be large. However, the fast increasing size of the on-chip storage based on traditional SRAM cells, such as register file (RF), shared memory and first level data (L1D) cache, makes the area cost and energy consumption unsustainable for future GPGPUs. In this paper, we first propose to use the embedded-DRAM (eDRAM) as an alternative for the on-chip storage. Compared to the conventional SRAM, eDRAM enables higher density and lower leakage power, but suffers from limited data retention time. Periodic refresh operation is a viable approach to maintain data integrity but aggravates the performance and energy consumption with the scaling of eDRAM cells into deep sub-micron technology nodes. To recover the performance loss, we exploit the features in the GPGPU architecture and propose various novel refresh schemes to mitigate the refresh penalty. To improve the energy efficiency, we apply lightweight compiler techniques and runtime monitoring for selective refreshing that intelligently eliminate the unnecessary refreshes. The evaluation on our proposed refresh schemes demonstrates that, comparing to the conventional SRAM-based designs, our eDRAM-based on-chip storage exhibits comparable performance but less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for even higher parallelism in future GPGPUs.

Impact of Total Ionizing Dose on the Data Retention of a 65 nm SONOS-Based NOR Flash

In this paper, the impact of total ionizing dose on the data retention behavior of a silicon-oxide-nitride-oxide-silicon-based NOR flash nonvolatile memory is studied for the first time on a deep sub-micron 65-nm complementary metal-oxide semiconductor technology node. The fundamental nonvolatile single-level cell memory element utilizes uniform Fowler-Nordheim (F-N) tunneling for both program and erase operations. The data retention behavior is investigated on a 4-Mb NOR Flash-based memory array at space-level total ionizing dose (TID) exposures up to 500 krad. Excessive TID exposure reduces the program-erase window but improves the thermal emission coefficient and, hence, improves data retention.

A 60 GHz Drain-Source Neutralized Wideband Linear Power Amplifier in 28 nm CMOS

CMOS technology scaling has enabled the design of high speed and efficient digital circuits. However, the continued scaling is detrimental to the design of RF and mm-wave systems. Higher sensitivity to process variations and inaccuracies in modeling of active and passive devices pose another challenge to the design of these systems at deep submicron technology nodes. This paper describes the design of a 60 GHz power amplifier in 28 nm CMOS technology. A drain-source neutralization technique maintains the stability of the PA and the wideband nature is achieved by the application of low-k transformer networks. The PA comprises of three stages and achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB. Using a two-way transmission line based power combiner, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%.

Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies

ABSTRACT Performance of high fan–in Domino circuits is degraded by technology scaling due to exponential increase in leakage. To improve the performance Current Comparison Domino (CCD) circuits are widely used. This work presents design of wide fan-in high performance current comparison domino circuits with goals of minimizing the power dissipation and propagation delay at 90nm and 45nm ultra deep submicron (UDSM) technology nodes. A Current Comparison Domino (CCD) 32-input wide footless OR gate circuit is employed for design and analysis work. Cadence GPDK 90nm & 45nm model parameters are used in this research work. Cadence Virtuoso schematic editor is used to draw the schematic and Spectre circuit simulator is used for simulation work. Layouts are generated in Virtuoso Layout editor. Pre-layout and post- layout simulation results are compared for validation of results. At 45nm technology, the Power consumption is 718.6nW, Propagation delay is 1.450ns and Power delay product (PDP) is 1.041fj. 92% improvement in power consumption at 45nm technology has been achieved as compared to previous work (at 16nm) by generating highly customized layout of the designed circuit.

Performance Optimization and Comparison of CNT Interconnect with Copper at VDSM Technology

As the CMOS process technology continues to scale, standard copper (Cu) interconnect will become a major hurdle for the best performance at very deep submicron (VDSM) technology node. The carbon nanotube (CNT) bundles have potential to provide an attractive solution for the higher resistivity and electromigration problems faced by traditional copper interconnects in VDSM technology node. This paper presents important guidelines to minimize the resistance, capacitance and inductance of a mixed CNT bundle interconnect for achieving best performance. The performance of mixed CNT bundle and copper is then compared at local and global interconnects level at 22nm technology node. HSPICE simulations carried out using Berkeley predictive technology model (BPTM) at an operating frequency of 1GHz, shows that for interconnect length of 1000um, the mixed CNT and optimized CNT (CNT_Opt) bundles are 1.98X and 2.20X faster, 74% and 84% more energy efficient respectively than the Copper interconnects.

Communication and migration energy aware task mapping for reliable multiprocessor systems

Heterogeneous multiprocessor systems-on-chip (MPSoCs) are emerging as a promising solution in deep sub-micron technology nodes to satisfy design performance and power requirements. However, shrinking transistor geometry and aggressive voltage scaling are negatively impacting the dependability of these MPSoCs by increasing the chances of failures. This paper proposes an offline (design-time) task remapping technique to minimize the communication energy and task migration overhead of an application mapped on a heterogeneous multiprocessor system for all processor fault-scenarios. The proposed technique involves two steps–(1) Communication Energy driven Design Space Exploration (CDSE) to select an initial mapping and (2) Communication energy and Migration overhead aware Task Mapping (CMTM) for different fault-scenarios. The CDSE is formulated as a Mixed Integer Quadratic Programming (MIQP) problem and solved using an energy-gradient based heuristic. The CMTM problem is solved using a fast heuristic with the starting mapping selected using CDSE step. The proposed two steps technique is compared with state-of-the-art approaches through rigorous simulations with synthetic and real application graphs. Results demonstrate that the proposed CDSE reduces design space exploration time by 99% with a maximum variation of 5% from the optimal solution obtained by solving the MIQP problem directly. Further, the proposed CMTM reduces communication energy by an average 35% and migration overhead by an average 20% for all single and double fault-scenarios as compared to the existing fault-tolerant techniques. The CMTM also achieves over 30x reductions in execution time for large problem sizes with a maximum deviation of 15% from the minimum communication energy achievable with the given application on a given architecture. For streaming multimedia applications, the proposed technique delivers 50% higher throughput per unit energy as compared to the existing approaches.

(Keynote) III-V Compound Semiconductor Field Effect Transistors for Low Power Digital Logic

As traditional Silicon transistor scaling fast approaches its limits alternate channel materials are being actively researched to enable a new era of power constrained Very Large Scale Integrated (VLSI) circuit design. The outstanding transport properties of compound semiconductor III-V materials make them very attractive candidates to continue scaling into deep sub-micron technology nodes beyond 14nm. However several key challenges need to be addressed in order for these new materials to replace state of the art Strained Silicon, High-k metal gate or Silicon on Insulator (SOI) technologies. This paper discusses the key issues involved and recent research highlights in III-V MOSFETs motivating their viability for future low power CMOS technology.

A novel sensitivity model for short nets

For modern processes at deep sub-micron technology nodes, yield design, especially the design at the layout stage is an important way to deal with the problem of manufacturability and yield. In order to reduce the yield loss caused by redundancy material defects, the choice of nets to be optimized at first is an important step in the process of layout optimization. This paper provides a new sensitivity model for a short net, which is net-based and reflects the size of the critical area between a single net and the nets around it. Since this model is based on a single net and includes the information of the surrounding nets, the critical area between the single net and surrounding nets can be reduced at the same time. In this way, the efficiency of layout optimization becomes higher. According to experimental observations, this sensitivity model can be used to choose the position for optimization. Compared with the chip-area-based and basic-layout-based sensitivity models, our sensitivity model not only has higher efficiency, but also confirms that choosing the net to be optimized at first improves the design.