SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

Abstract

This work presents a novel low-leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep submicron technology nodes, it includes static noise margin monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of the first failure. As proof of concept, a macro of 1 Mb is fabricated in 22-nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.