Deep Submicron Regime Research Articles

Design Issues in Intercalation-Doped-Multilayer Graphene Nanoribbon-Based Future Interconnects in Deep Submicron Regime

Intercalation-doped multilayer graphene nanoribbon (ID-MLGNR) is a potential contender for future interconnect applications. This work presents a comprehensive analysis of temperature-dependent design issues in ID-MLGNR-based future VLSI interconnects based on a temperature-dependent mean free path (MFP) model incorporating scattering owning to rough edges and defects in GNRs, which consequently reflects the extrinsic temperature-dependent circuit behavior of these interconnects in terms of wire impedance, propagation delay, and power dissipation. It is found that in deep submicron (DSM) regime, at a specific technology node of 14-nm MFP, edge scattering improves by 74% as Fermi energy ([Formula: see text] increases from 0.2 to 0.6, and at a specularity constant, [Formula: see text] for local and intermediate level of interconnects. For similar values of [Formula: see text] and [Formula: see text], at global length, this rise in MFP is about 70%, which signifies the significant reduction in resistance (varies inversely to MFP). Whereas, negligible variations are observed in the conductance and inductance of ID-MLGNR interconnects with an increase in temperature. Nevertheless, the reduction in resistance for local & intermediate, and global MLGNR interconnects reflects its low propagation delay and power-delay-product (PDP) for future VLSI ICs applications despite the negligibly poor decrease in power dissipation (with an overall % reduction in the power dissipation from 300[Formula: see text]K to 500[Formula: see text]K evaluated to 3.54% regardless increase in [Formula: see text] from 0.2[Formula: see text]eV to 0.6[Formula: see text]eV).

Tunnel field effect transistor device structures: A comprehensive review

Downscaling of metal oxide semiconductor field effect transistors (MOSFET) has resulted in increased short channel effects (SCEs), off-leakage current and subthreshold swing. At room temperature, the minimum subthreshold swing for MOSFETs is 60 mV/dec. So, MOSFET is not suitable for the deep submicron regime. A new device structure is being investigated to overcome the limitations of MOSFETs. The tunnel field effect transistor is the new emerging device (TFET). TFETs are the most suitable candidate for low power applications due to their superior performance, such as low power dissipation, low leakage current, and subthreshold swing (SS) less than 60 mV/dec. Ambipolar effect is the main cause of high Ioff current, this effect can be reduced by the asymmetry in structure and varied doping in source and drain. As a result, the Ioff current in the TFET may be reduced and the Ion/Ioff current ratio can be increased. TFET is a simple p-i-n structure with reversed bias at the gate terminal and works on the principle of the band to band tunneling (BTBT). The basic structure of TFET also suffers from low Ion current. However, with the variation of physical parameters in structure, the Ion current can be improved. This paper reviews the physical parameters of TFET and their impact as well as different structures of TFET like surface tunnel transistors, p-i-n structure TFET, Junctionless TFET, and Dual gate TFETs, Heterojunction TFETs, Vertical TFETs, PNPN TFET, and Nanowire TFET.

Performance Analysis of 6T SRAM and ONOFIC Cells

Background: As the technology node scales down to a deep sub-micron regime, the design of static random-access memory (SRAM) cell becomes a critical issue because of increased leakage current components. These leakage current components prevent the designing of a low-power processor as a large portion of the processor power is consumed by the memory part. Objective: In this paper, an SRAM cell is designed based on the ON/OFF logic (ONOFIC) approach. Static noise margin (SNM) of the cell for the different states are calculated and evaluated by using the butterfly as well as noise (N) curves with the help of Cadence tools at 45 nm technology node. Methods: ONOFIC approach reduces the leakage current components, which makes a low power memory cell. A performance comparison is made between the conventional six-transistor (6T) SRAM cell and memory cell using the ONOFIC approach. Results: Low value of power delay product (PDP) is the outcome of the ONOFIC approach as compared to conventional cells. ONOFIC approach decreases PDP by 99.99% in case of hold state. Conclusions: ONOFIC approach improves the different performance metrics for the different states of the SRAM cell.

Comparison of Fitting Current–Voltage Characteristics Curves of FinFET Transistors with Various Fixed Parameters

In the deep submicron regime, FinFET successfully suppresses the leakage current using a 3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate is applied with a bias wholly wrapping the channel. Fortunately, a scanning photo-lithography using extensive ultraviolet (EUV) and multi-mask task carefully resolves critical dimension issues. The ensuing anisotropic plasma dry etching is somehow a subsequent challenging process, which consumes the edge of original ‘I’-shape epitaxial silicon and causes dimension loss, and thus produces fin-like bodies as prepared channels. In order to protect the transistors from malfunction due to dimension over-etching, fin width is taken to be 120 nanometers, while the channel lengths vary. The prepared transistors are measured and characteristic curves are fitted for analysis. Measured current versus voltage characteristic curves are fitted with three parameters (transistor geometry constant, threshold voltage, and Early voltage) in the conventional current-voltage formula, which are allowed to vary as the short channel effects or process-related issues are taken into account. In this paper, one of the three is deliberately set to be fixed for a transistor, and the others are freely chosen and determined to reach minimum variation. Various conclusions through comparisons and analysis may give important feasible applications in the future.

Dielectric surface roughness scattering induced crosstalk performance of coupled MCB interconnects

A CMOS inverter driven equivalent single conductor model of capacitively coupled mixed CNT bundle (MCB) interconnects are taken to analyze the crosstalk induced time domain and frequency domain behaviors at 14 nm technology node for a temperature range (300–500 K). Four possible structures of MCB (e.g.S1, S2, S3 & S4) are analyzed by considering the dielectric substrate materials induced scattering. The most typical and consistent dielectric materials like silicon dioxide (SiO2), boron nitride (BN) and silicon carbide (SiC) are taken into account for studying the behavior of MCB depending upon dielectric surface roughness (DSR) scattering. A complete crosstalk (dynamic & functional) effect in terms of positive peaks, time duration and area of rise glitch is studied. The results revealed that MCB structure ‘S4’ is having less delay and more 3-dB frequency bandwidth in comparison to other structures of MCB. Moreover, S4 placed on SiC substrate material is depicting best results among other substrate materials. The bode stability of ‘S4’ on smooth surface and rough surface material is analyzed to validate the performance of ‘S4SiC’ in terms of phase and gain margin. It is also observed that the 3-dB frequency bandwidth of ‘S4SiC'reduces with increase in temperature. Consequently, the amplitude of surface roughness parameter (δsr) plays an important role to analyze the performance of coupled interconnects of MCB in deep sub-micron (DSM) regime.

WITHDRAWN: Dynamic switching analysis of coupled RLC interconnects with physical and environmental variations

Abstract With continuous downscaling of integrated circuits into deep submicron and nanometer regime, operating at high frequencies, it has become most important to evaluate the reliability and efficiency of on-chip interconnects. The study of device and dynamic variations on dynamic crosstalk in inductive coupled interconnect wires is discussed in this paper. It analyses and studies the effect of driver size, interconnect length, supply voltage and temperature on the coupled interconnect lines. In the analysis, single and cascaded repeaters are used to drive the coupled interconnect lines. For local interconnects, as the driver size increases from 1X to 4X, the propagation delay decreases by 70.9% and the power dissipation increases by 5.75%. For global interconnects, as length of the interconnect increases from 1 mm to 2.5 mm, power dissipation and propagation delay are increased by 56.77% and 51.93% respectively. Analysis of variation of supply voltage and operating temperature is also carried out in this work. The analysis is carried out using geometric dimensions and the impedance parameters of copper interconnect extracted from PTM models for 45 nm CMOS technology node.

Design and Simulation of Reliable Low Power CMOS Logic Gates

In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by ≈81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit.

WITHDRAWN: Impact of device and dynamic variations on functional crosstalk noise and delay in inductively coupled interconnects

With continuous downscaling of integrated circuits into deep submicron and nanometer regime, operating at high frequencies, it has become most important to evaluate the reliability and efficiency of on-chip interconnects. The study of device and dynamic variations on functional crosstalk in inductive coupled interconnect wires is discussed in this paper. It analyses and studies the effect of driver size and temperature on the coupled interconnect lines. In the analysis, single and cascaded repeaters are used to drive the coupled interconnect lines. The study reveals that the maximum positive forward crosstalk noise of the cascaded repeater driven interconnect is 33.61 percent smaller than the peak positive forward crosstalk noise of minimum sized single repeater driven interconnect. The variation in supply voltage and temperature impacts the propagation delay and power dissipation of coupled interconnects. It is observed that the propagation delay decreases, and power dissipation increases with increase in supply voltage. It is also evaluated that the propagation delay of the coupled interconnect increases with increase in temperature for the combined range of commercial and military applications ranging from −55 °C to 125 °C. The analysis is carried out using geometric dimensions and the impedance parameters of copper interconnect extracted from PTM models for 45 nm CMOS technology node.

Bootstrapped Driver and the Single-Event-Upset Effect

As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumed. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single-event upsets (SEU), which are known to affect DSM circuits working under low voltages. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles.

Relative stability of shielded top- and side-contact MLGNR interconnects

ABSTRACT In a recent nano and deep-submicron regime, the electromagnetic interference primarily plays an important role in determining the overall interconnect performance of an integrated circuit (IC). For instance, it can cause lower reliability, and stability in silicon technology. In order to mitigate these challenges, this work introduces a new technique of active shielding by introducing a jacketed side- (SC) and top-contact (TC) multi-layered graphene nanoribbon (MLGNR) interconnect to demonstrate the relative stability. Depending on the physical configuration, an accurate Pi-type electrical network is proposed for the shielded TC-and SC-MLGNR at 32 nm technology. Using the equivalent circuit model, a fifth-order transfer function is employed to demonstrate the relative stability of SC- and TC-MLGNR at global interconnect lengths.

Thermal gradients and anomalous Nernst effects in membrane-supported nonlocal spin valves

Metallic nonlocal spin valves (NLSVs) are important in modern spintronics due to their ability to separate pure spin current from charge current. These metallic nanostructures, often constructed from features with widths in the deep submicron regime, generate significant thermal gradients in operation, and the heat generated has important consequences for spin injection and transport. We use e-beam nanolithography to manufacture NLSVs with Ni-Fe alloy ferromagnetic nanowires and aluminum spin channels on 500-nm silicon nitride (Si-N) membranes to lower the thermal conductance of the substrate dramatically. While this extreme example of thermal engineering in a spintronic system increases the background nonlocal signals in ways expected based on earlier work, it also enhances thermoelectric effects, including the anomalous Nernst effect, and reveals a previously unknown thermally assisted electrical spin injection that results from a purely in-plane thermal gradient. We examine these effects as a function of temperature and, by careful comparison with 2D finite element models of the thermal gradients calculated at a single temperature, demonstrate that the anomalous Nernst coefficient of the 35-nm-thick Ni-Fe alloy, ${R}_{\mathrm{N}}=0.17$ at $T=200\phantom{\rule{4pt}{0ex}}\mathrm{K}$, is in line with the few previous measurements of this effect for thin films.

A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates

In this work, a new technique for domino circuit is proposed to reduce the process variations and power dissipation with optimized delay for wide fan-in OR logic. Two methods are used to reduce both process variation and power dissipation at the same time. In first part, the keeper circuit has been redesigned to reduce the process variation with enhanced noise margin. And in second part, evaluation network has been redesigned to reduce the subthreshold leakage current at optimized delay. Thus, the proposed domino can be used to design the low power VLSI circuits and deep submicron regime. The simulation results show that this work exhibits about 64% and 30% process variations reduction in power, and 38% and 21% process variations reduction in delay for reported conventional domino and a simple approach for delay reduction domino respectively. Noise margin is also improved by 1.41 and 1.16 times compared to above said schemes respectively. All simulation results are obtained with Cadence Virtuoso environment using SPECTRE simulator for 45 nm CMOS technology.

Research and Implement of Cache Fault Tolerance Technique

For the space application, cache rams are easy to be affected by single event upset (SEU). To protect against SEU error, it is necessary to design fault tolerance cache. Multiple bit-flips faults are increasing as integrated circuits continue to scale into the deep sub-micron regime, the error detection ability need to be improved, so an interleaving grouping parity error detection code scheme is proposed in this paper, each 32-bit data and each 19-bit tag adding 4 valid bits adopt 4 parity bits respectively, the adjacent 4 bits data are assigned to different groups, so all less than 8 bits burst faults can be detected. The hit structure and updating structure of the cache memory are redesigned. No timing penalty occurs since parity checking is performed in parallel with tag comparison. The experimental results show that, by using the proposed technique, there is a small performance loss, but the advantage is the higher reliability valuable for safety system. The failure rate of the cache memory is lower by 6 orders of magnitude.

A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems

Rapid advancement in deep sub-micron regime has made the integration of multiple processing elements possible on a single chip. This has enabled parallel execution of applications on Network-on-Chip (NoC) based multiprocessor platforms. Task mapping and scheduling play crucial roles in timing response and energy consumption of such systems. Tasks present in these applications can be of mixed critical in nature with different importance. However, the on-chip processors executing these tasks of any given application might fail during runtime. Fault tolerance becomes challenging when real-time applications with mixed critical requirements are hosted on such fault prone environment. The complexity of the problem is further magnified in dynamic scenarios when such real-time applications can enter or leave the multicore platform at any time instant. Although several prior works have addressed fault tolerant resource allocation for mixed critical applications, few of these consider permanent processor faults. In this work, an improved fault tolerant resource allocation strategy is presented to mitigate the effect of permanent processor faults on mixed critical applications. The proposed algorithm offers a runtime solution to the unified problem of fault tolerant mapping and scheduling for real-time applications. Both the temporal property of the tasks and the timing information of the faults have been considered while implementing a suitable fault tolerance strategy that reduces the communication energy consumption and provides an improved level of quality of service for the executing applications. A detailed evaluation of the performance of the proposed algorithm has been conducted for different applications. On comparing with other state-of-the-art fault tolerant approaches, the proposed policy shows 28.5% average reduction in communication energy consumption while achieving 34.7% improved quality of service. Additionally, the proposed scheme shows better scalability in comparison to the recent techniques reported in literature.

A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits

A new leakage tolerant high speed domino gate having higher noise immunity, low power dissipation, and less process variations for wide fan-in OR logic is developed. This paper deals with the design of a high speed comparator based domino gate with low leakage that decides the output on the basis of voltage difference across the pull down network. In order to design mirror of voltage comparator, PMOS is replaced by NMOS for low process variation. Furthermore, stacking of NMOS is accomplished to reduce leakage and total current transfer in cascode fashion. Hence, the proposed domino can be operated in deep submicron regime. The simulation results confirm that the proposed domino gate exhibits about 17.58% power dissipation reduction and 1.21 times noise immunity improvement in contrast with reported voltage comparison based domino. The simulation results are achieved with Cadence Virtuoso environment using SPECTRE simulator in 45 nm CMOS technology.

QCA Gray Code Converter Circuits Using LTEx Methodology

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The “defect-tolerant analysis” of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

On the Restore Time Variations of Future DRAM Memory

As the de facto main memory standard, DRAM (Dynamic Random Access Memory) has achieved dramatic density improvement in the past four decades, along with the advancements in process technology. Recent studies reveal that one of the major challenges in scaling DRAM into the deep sub-micron regime is its significant variations on cell restore time, which affect timing constraints such as write recovery time. Adopting traditional approaches results in either low yield rate or large performance degradation. In this article, we propose schemes to expose the variations to the architectural level. By constructing memory chunks with different access speeds and, in particular, exploiting the performance benefits of fast chunks, a variation-aware memory controller can effectively mitigate the performance loss due to relaxed timing constraints. We then proposed restore-time-aware rank construction and page allocation schemes to make better use of fast chunks. Our experimental results show that, compared to traditional designs such as row sparing and Error Correcting Codes, the proposed schemes help to improve system performance by about 16% and 20%, respectively, for 20nm and 14nm technology nodes on a four-core multiprocessor system.

State Asymmetry Driven State Remapping in Phase Change Memory

Phase change memory (PCM) is one of the most promising candidates to replace DRAM as main memory in deep submicron regime. Regardless of single-level or multiple-level cells, the programming costs to each state exhibit significant asymmetries in latency, energy and endurance. In this paper, we exploit the potential of reducing programming costs in terms of latency, energy, and endurance for PCM through state remapping. First, quantitative programming models are constructed for cost assessments. Then, both dynamic and static remapping schemes are analyzed and compared. The observation that the efficacy of dynamic state remappings is instable motivates us to propose a static remapping technique, which outperforms previous work in cost reduction within much lower implementation overhead. The optimality of the proposed static state remapping is also proved. The evaluation results confirm the efficacy of the proposed state remapping technique in delivering a stable and promising cost reduction in latency, energy, and wear.

An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures

Modern systems-on-chip (SoCs) today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs) use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM) is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture.

SD-PCM

Phase Change Memory (PCM) has better scalability and smaller cell size comparing to DRAM. However, further scaling PCM cell in deep sub-micron regime results in significant thermal based write disturbance (WD). Naively allocating large inter-cell space increases cell size from 4F 2 ideal to 12F 2 . While a recent work mitigates WD along word-lines through disturbance resilient data encoding, it is ineffective for WD along bit-lines, which is more severe due to widely adopted $\mu$Trench structure in constructing PCM cell arrays. Without mitigating WD along bit-lines, a PCM cell still has 8F2, which is 100% larger than the ideal. In this paper, we propose SD-PCM for achieving reliable write operations in super dense PCM. In particular, we focus on mitigating WD along bit-lines such that we can construct super dense PCM chips with 4F 2 cell size, i.e., the minimal for diode-switch based PCM. Based on simple verification-n-correction (VnC), we propose LazyCorrection and PreRead to effectively reduce VnC overhead and minimize cascading verification during write. We further propose (n:m)-Alloc for achieving good tradeoff between VnC overhead minimization and memory capacity loss. Our experimental results show that, comparing to a WD-free low density PCM, SD-PCM achieves 80% capacity improvement in cell arrays while incurring around 0-10% performance degradation when using different (n:m) allocators.