A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits

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A new leakage tolerant high speed domino gate having higher noise immunity, low power dissipation, and less process variations for wide fan-in OR logic is developed. This paper deals with the design of a high speed comparator based domino gate with low leakage that decides the output on the basis of voltage difference across the pull down network. In order to design mirror of voltage comparator, PMOS is replaced by NMOS for low process variation. Furthermore, stacking of NMOS is accomplished to reduce leakage and total current transfer in cascode fashion. Hence, the proposed domino can be operated in deep submicron regime. The simulation results confirm that the proposed domino gate exhibits about 17.58% power dissipation reduction and 1.21 times noise immunity improvement in contrast with reported voltage comparison based domino. The simulation results are achieved with Cadence Virtuoso environment using SPECTRE simulator in 45 nm CMOS technology.