Research and Implement of Cache Fault Tolerance Technique

Abstract

For the space application, cache rams are easy to be affected by single event upset (SEU). To protect against SEU error, it is necessary to design fault tolerance cache. Multiple bit-flips faults are increasing as integrated circuits continue to scale into the deep sub-micron regime, the error detection ability need to be improved, so an interleaving grouping parity error detection code scheme is proposed in this paper, each 32-bit data and each 19-bit tag adding 4 valid bits adopt 4 parity bits respectively, the adjacent 4 bits data are assigned to different groups, so all less than 8 bits burst faults can be detected. The hit structure and updating structure of the cache memory are redesigned. No timing penalty occurs since parity checking is performed in parallel with tag comparison. The experimental results show that, by using the proposed technique, there is a small performance loss, but the advantage is the higher reliability valuable for safety system. The failure rate of the cache memory is lower by 6 orders of magnitude.