Deep Submicron Channel Lengths Research Articles

Deep-Submicron Channel Length Oxide Semiconductor Thin-Film Transistors Enabled by Self-Aligned Nanogap Lithography

Deep-Submicron Channel Length Oxide Semiconductor Thin-Film Transistors Enabled by Self-Aligned Nanogap Lithography

48‐1: Invited Paper: Oxide Semiconductor Thin‐Film Transistors with Deep Submicron Channel Fabricated with Hyperlithography

We propose and present in detail the new method to enable the deep submicron channel length in oxide semiconductor thin‐film transistors with conventional lithographic tool in large‐area substrates. Up till now we succeeded in fabricating the oxide thin‐ film transistors with 60 nm channel length with the performance of ~300 µA/µm at a drain bias of 1.5 V, and gate bias of 2 V, ION/IOFF larger than 109, subthreshold swing of 100 mV/dec, and turn‐on voltage of about ‐0.47 V . We hope that our technique will contribute to open a new era as a backplane technology for transparent ultra‐high‐resolution displays such as hologram, AR, and/or XR.

(Invited) Metal Oxide Thin-Film Transistors with Deep Submicron Channel Enabled By Self-Aligned Nano Gap Patterning

We demonstrate the fabrication technology of metal oxide semiconductor thin-film transistors (TFTs) with deep submicron channel length and their electrical characterization. We call the method as self-aligned nano gap patterning (SANP), where the pattern resolution is limited not by optical diffraction in photolithography, but by the details in etching and deposition process. Therefore, this makes it enable to overcome the obstacle in the scale down of large area electronic devices, for which high resolution photolithography tools such as VUV or XUV used in semiconductor industry are almost useless due to the extremely low throughput and high cost. In this work, we employ the contact aligner with line and space resolution of 3 μm, and the oxides TFTs with 0.1μm channel length was successfully fabricated with field-effect mobility of 12 cm2/Vs, subthreshold swing of 100 mV/dec, Ion/Ioff of 1010, and turn-on voltage of -0.88 V.

Performance evaluation of channel length downscaling of various high voltage AlGaN/GaN power HEMTs

Channel length downscaling characteristics of various lateral AlGaN/GaN high electron mobility transistors (HEMTs) are simulated. Quasi‐constant‐field scaled MOS channel HEMTs show superior performance over two‐dimensional electron gas (2DEG) channel HEMTs at deep submicron channel lengths. The adverse effects of deep submicron channel length on threshold voltage, drain‐induced barrier lowering, subthreshold swing, transconductance and on‐off current ratio are seen to be much less pronounced in MOS channel HEMTs compared with 2DEG channel HEMTs. Switching capabilities of enhancement mode HEMTs at different channel lengths are evaluated and compared using a new intrinsic maximum switching frequency (fm,IG) figure‐of‐merit.

Analytical Drain Thermal Noise Current Model Valid for Deep Submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.

SiGe(C) epitaxial technologies—issues and prospectives

Epitaxial layers of SiGe(C) have entered mainstream Si processing—forming base regions in heterojunction bipolar transistors. There are also exciting prospects that SiGe(C) could impact MOS technologies. In both cases heteroepitaxial layers enable very significant performance enhancements at device and circuit level. A related area and a familiar hot-potato is silicon epitaxy for device active regions in MOS technologies—where tightly controlled doping distributions can be incorporated to facilitate device function at deep submicron channel lengths. CVD is a preferred epitaxy deposition technique for production—currently LP-CVD and UHV-CVD dominate. Each of these techniques demand much of the technology and have their respective strengths and weaknesses. Issues regarding matrix and doping control, uniformity, blanket and selective area growth and throughput (a sensitive area) will be addressed. Also in the CVD portfolio is LEPE-CVD—a recent contender for the production arena which has the facility of being able to access very high deposition rates as required for example in depositing relaxed buffer layer material required as ‘virtual substrates’ for higher Ge content layers. SS-MBE, traditionally the favourite technique for research, also has distinct possibilities for development as a production tool. Here the issues relate primarily to throughput and system design, and (surprisingly) matrix profile control. These techniques will be outlined and reviewed along with issues which determine their development as the competition hots up in epitaxy, and as more complex and high Ge content structures are needed to progress Si technology to new performance heights and application areas.

A new unified model for submicron MOSFETs

A new unified analytical model for submicron MOSFETs, valid for all regions of operation (including deep subthreshold), is presented in this paper. It accounts for the changes in the subthreshold slope with respect to the applied drain voltage. A new unification technique is proposed, which preserves the continuity of the drain current and its derivatives with respect to the applied terminal voltages at the various operating region boundaries. It passes the benchmark tests of Tsividis and Suyama (IEEE J. Sol. St. Circ., 29 (1994) 210–216) adequately, and thus, is suitable for analog circuit computer-aided design work. Also, the simulated results match well with the experimental results for deep submicron channel length devices.

New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.

A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset

A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated. The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution. The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.

Impact of distributed gate resistance on the performance of MOS devices

This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of f/sub T/ is proven to be independent of gate resistance even for distributed structures. An exact relation for f/sub max/ is derived and it is shown that, to predict f/sub max/, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal. >

Influence of statistical dopant fluctuations on MOS transistors with deep submicron channel lengths

The influence of statistical doping fluctuations on the threshold voltage of a MOS transistor is examined. It is found that for transistors with a channel area of less than 0.1μm 2 (corresponding to a channel length of 0.1μm with a W/L ratio of 10) statistical doping fluctuations will result in significant fluctuations of the threshold voltage.