Deep-submicrometer CMOS Technology Research Articles

A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology

Despite the scaling of the supply voltage of deep-submicrometer CMOS technologies, many applications still require to deal with off-chip signals in high-voltage domains (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5~ \mathrm{V})$</tex-math> </inline-formula> . Hence, foundries offer fabrication processes with voltage-tolerant transistors, which are inherently protected from the electrical stress, at the expenses of compromising their performances, reducing the design portability, and augmenting the production costs in case of the customization of the process. As an alternative, circuit techniques, such as cascoding, adaptive biasing, and voltage shifting, result effective in designing analog circuits, such as amplifiers and voltage drivers at high supply voltage with voltage-scaled transistors. This article presents the architecture of a switch for analog multiplexers (MUXs) able to handle signals up to twice the nominal supply voltage of the employed transistors. To validate the circuit choice, a switch for a 5-V MUX has been designed with 2.5-V transistors in 28-nm CMOS technology. The comparison with a benchmark architecture with tailored 5-V devices shows that an about three times larger area and 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A static current demand have to be considered. Moreover, an accelerated degradation test (ADT) showed a similar decay of the features of both types of switches.

Simple Technique to Improve Essentially the Performance of One-Stage Op-Amps in Deep Submicrometer CMOS Technologies

A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged.

Recent Developments and Design Challenges of High-Performance Ring Oscillator CMOS Time-to-Digital Converters

Time-to-digital converters (TDCs) are increasingly used as building blocks in biomedical imaging, digital communication, and measurement instrumentation systems. When fabricated in deep-submicrometer (DSM) CMOS technology, TDCs have outstanding time stamping capability on the order of picoseconds. Typically, the timing resolution of a TDC directly determines the minimum resolvable spatial resolution in time-of-flight (ToF) measurements. It also limits the signal-to-noise ratio in ToF positron emission tomography and the in-band noise in an all-digital phase-locked-loop. In TDCs, good linearity and precision result in high measurement accuracy, while the detectable range is limited by its dynamic range. In addition, size and power consumption are of significant importance in large-scale array implementations such as image sensors. Here, we discuss the most recent developments in CMOS TDCs, with an emphasis on ring-oscillator-based TDC and its variants, due to their suitability for array designs with less area overhead. In addition, key performance metrics, and accurate cost-effective characterization methods will be discussed. Finally, future perspectives of CMOS TDCs will be highlighted.

A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

This paper presents a design methodology for an ultra-low-power (ULP) and ultra-low-voltage (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed and a new biasing metric for ULV and ULP designs in deep-submicrometer CMOS technologies is introduced. Series inductive peaking in the feedback loop is analyzed and employed to enhance the bandwidth and noise performance of the LNA. Exploiting the new biasing metric, the design methodology, and series inductive peaking in the feedback loop, a 0.5 V, 0.75-mW broadband LNA with a current reuse scheme is implemented in a 90-nm CMOS technology. Measurement results show 12.6-dB voltage gain, 0.1–7-GHz bandwidth, 5.5-dB NF, −9-dBm IIP $_{3}$ , and −18-dB P1dB while occupying 0.23 mm $^{2}$ .

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-μm CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2V. A front-end system has been fabricated in a 90nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.

RF-Noise Modeling in Advanced CMOS Technologies

RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based on Nyquist's law, predictive modeling of thermal noise in MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess noise starts to play a significant role and its incorporation in thermal noise models is unavoidable. Here, we will review several crucial ingredients for accurate RF noise modeling, with emphasis on sub-100-nm technologies. In particular, a detailed derivation and discussion are presented of our microscopic excess noise model. It is shown to qualitatively explain the observed noise (across bias and geometry) in a wide range of commercially available sub-100-nm foundry processes. Besides, the impact of excess noise on the minimum noise figure is discussed.

A Novel, High-Dynamic-Range, High-Speed, and High-Sensitivity CMOS Imager Using Time-Domain Single-Photon Counting and Avalanche Photodiodes

Avalanche photodiodes used in Geiger mode as single-photon counters have become very attractive imaging tools. High-speed single-photon imaging can be used in very low-light-level applications such as surveillance and security imaging, quantum computing, and biomedical imaging including bioluminescence and fluorescence lifetime imaging. However, a typical avalanche-based single-photon detector cannot offer the high dynamic range that is needed for many biomedical and surveillance applications. In this paper, we show how a single-photon detector can be used in time domain for high-dynamic-range applications. We also discuss novel techniques to implement the time-domain single-photon imager in mainstream deep-submicrometer CMOS technology. The designed imager offers high dynamic range and high sensitivity, while maintaining high-speed operation and low cost.

Experimental Demonstration and Modeling of Excess RF Noise in Sub-100-nm CMOS Technologies

Accurate modeling of thermal noise in MOSFETs is crucial for RF application of deep-submicrometer CMOS technologies. Here, we present RF noise measurements on four commercial advanced CMOS technologies down to the 45-nm node. Based on this extensive set of measurements, we prove the existence of excess noise (i.e., above the pure Nyquist level), but at the same time, we show that it is significant only for sub-100-nm MOSFETs. The amount of excess noise depends mainly on the channel length, and its occurrence is remarkably universal across technologies. We also present an electric-field-dependent extension of Nyquist's law that represents a nonequilibrium-transport correction to diffusive transport. We show that this microscopic model quantitatively explains the main features of the experimentally observed excess noise for all technologies. This includes its bias dependence, its geometrical scaling behavior, and the observed difference between n-channel and p-channel devices.

$f_{\max}$ Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

In this letter, f max improvement of a circuit-level radio-frequency (RF) transistor with systematic layout variations is presented in deep-submicrometer CMOS technology. We confirmed that the circuit-level MOS transistor has a tradeoff among the extrinsic capacitive and resistive parasitics (C gd, C gs, and Rg) on circular gate metal layers. Furthermore, it reduces the extrinsic C gd and Rg, which have great effect on the RF performance, simultaneously. For qualitative analysis of the capacitive coupling, which attributed to undesired extrinsic capacitance, capacitive coupling paths were separately defined as two cases, namely, direct capacitive coupling and indirect capacitive coupling. Some of the key small-signal parameters were also extracted and compared with different types of transistors, and they show a good match with the observed trends. The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.

A 27 GHz, 14 dBm CMOS Power Amplifier Using 0.18 $\mu {\rm m}$ Common-Source MOSFETs

A Ka-band three-stage CMOS power amplifier was designed and fabricated using 0.18 mum gate-length common-source transistors. For low loss and accurate matching networks for the amplifier, a substrate-shielded microstrip-line was used with good modeling accuracy up to 40 GHz. The measured insertion loss was 0.5 dB/mm at 25 GHz. The three-stage amplifier achieved a 14.5 dB small-signal gain, 14 dBm output power, and 13.2% power-added-efficiency at 27 GHz in a compact chip area of 0.84 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured gain was the highest for Ka-band power amplifiers using common-source transistors. These results were achieved at a voltage compatible with deep sub-micrometer CMOS technology.

A 900-MHz 29.5-dBm 0.13-μm CMOS HiVP Power Amplifier

Using ST 0.13-mum CMOS technology, a class A power amplifier has been developed for the global system for mobile communication in Europe. To solve the problem of low breakdown voltage in deep-submicrometer CMOS technology, the high-voltage/high-power (HiVP) device configuration is used. With the HiVP configuration, a large voltage can be divided by several devices so that the voltage drop on each device can be limited under the breakdown voltage. The measurement results show that the output power of 29.5 dBm has been achieved at the frequency of 900 MHz. The linear power gain reaches 11.5 dB and the maximum power-added efficiency is as high as 34.5%.

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.

Influence of the Tunneling Gate Current on C-V Curves

This paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region.

Color mixing improvement of CMOS image sensor with air-gap-guard ring in deep-submicrometer CMOS technology

In this letter, color mixings of a CMOS image sensor with air-gap-guard-ring (AGGR) and conventional structures were investigated in 0.18-/spl mu/m CMOS image sensor technology. As the light incident angle is increased from 0/spl deg/ to 15/spl deg/, conventional pixel shows serious color mixing. For example, the maximum photo responses of blue, green1, green2, and red pixels are shifted from 490 to 520 nm, 530 to 500 nm, 530 to 600 nm, and 600 to 580 nm, respectively. However, pixels with AGGR not only keep correct spectral response without peak shift but also achieve 5%-50% crosstalk reduction, thus preventing the sensor from color mixing efficiently.

Digital Calibration for Monotonic Pipelined A/D Converters

The original digital calibration approach for 1 b/stage and 1.5 b/stage pipeline analog-digital converters produces missing or nonmonotonic digital codes with the device and circuit impairments typical of modern deep submicrometer CMOS technologies. Two digital calibration algorithms are introduced to improve pipeline performance when using low-voltage low-gain nonlinear operational amplifiers and high random dc offset voltage comparators. The first technique computes calibration coefficients for each stage at actual transition points of the residue characteristic to assure converter monotonicity in the presence of random comparator offset voltages. The second augments a conventional pipelined architecture with an input-dependent level-shifting stage and additional digital calibration circuitry to achieve high differential and integral linearity with low-gain nonlinear operational amplifiers.

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual V/sub t/ technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low V/sub t/ is applied properly.

The challenge of signal integrity in deep-submicrometer CMOS technology

Advances in interconnect technologies, such as the increase in the number of metal layers, stacked vias, and the reduced routing pitch, have played a key role to continuously improve integrated circuit design and operating speed. However several parasitic effects jeopardize the benefits of scale-down. Understanding and predicting interconnect behavior is vital for designing high-performance integrated circuit design. Our paper first reviews the interconnect parasitic effects and examines their impact on circuit behavior and their increase due to lithography reduction, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay. The problem of signal integrity characterization is then discussed. In our review of the different well-established measurement methodologies such as direct probing, S-parameters, e-beam sampling and on-chip sampling, we point out weaknesses, frequency ranges, drawbacks, and overall performances of these techniques. Subsequently, the on-chip sampling system is described. This features a precise line-domain characterization of the voltage waveform directly within the interconnect and shows its application in the accurate evaluation of propagation delay, crosstalk, and crosstalk-induced delay along interconnects in deep-submicrometer technology. The sensor parts are described in detail, together with signal integrity patterns and their implementation in 0.18-/spl mu/m CMOS technology. Measurements obtained with this technique are presented. In the third part, we discuss the simulation issues, describe the two- and three-dimensional interconnect modeling problems, and review the active device models applicable to deep-submicrometer technologies in order to agree on measurements and simulations. These studies result in a set of guidelines concerning the choice of interconnect models. The last part outlines the design rules to be used by designers and their implementation within computer-aided design (CAD) tools to achieve signal integrity compliance. From a 0.18-/spl mu/m technology are derived critical variables such as crosstalk tolerance margin, maximum coupling length, and the criteria for adding a signal repeater. From these, values for low-dielectric and copper interconnects have been selected.

RF circuit performance degradation due to soft breakdown and hot-carrier effect in deep-submicrometer CMOS technology

A systematic study of RF circuit performance degradation subject to oxide soft breakdown (SBD), and hot-carrier (HC) stress is presented in this paper. DC and RF characteristics before and after stress are extracted from the experimental data. The effects of SBD and HC stress on s-parameters, cutoff frequency, third-order interception point, and noise parameters are examined. The performance drifts of gain, noise figure, linearity, and input matching of the RF low-noise amplifier are demonstrated by SpectreRF simulation results based on measured device data.