$f_{\max}$ Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

Abstract

In this letter, f max improvement of a circuit-level radio-frequency (RF) transistor with systematic layout variations is presented in deep-submicrometer CMOS technology. We confirmed that the circuit-level MOS transistor has a tradeoff among the extrinsic capacitive and resistive parasitics (C gd, C gs, and Rg) on circular gate metal layers. Furthermore, it reduces the extrinsic C gd and Rg, which have great effect on the RF performance, simultaneously. For qualitative analysis of the capacitive coupling, which attributed to undesired extrinsic capacitance, capacitive coupling paths were separately defined as two cases, namely, direct capacitive coupling and indirect capacitive coupling. Some of the key small-signal parameters were also extracted and compared with different types of transistors, and they show a good match with the observed trends. The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.