Deep Submicron Technologies Research Articles

Plasmonic image reproduction with solid-state superionic stamping (S4)

Traditional top-down approaches for producing metallic nanostructures, despite being capable of producing arbitrary 2-D shapes, often use vacuum-based deep sub-micron lithographic fabrication technologies. This makes their use for single-use devices like chemical and bio-sensing substrates difficult to economically justify. Here, the authors demonstrate a manufacturing pathway that only uses such techniques to produce a master. This reusable master, coupled with a unique and facile electrochemical imprinting process, Solid-State Superionic Stamping (S4), is used to produce several replicated metallic nanostructures, thus demonstrating an economically feasible manufacturing pathway for single-use, nano-enabled devices.This paper uses plasmonic image reproduction as an easy-to-visualize proxy for single-use devices such as plasmonic sensors and Surface Enhanced Raman Spectroscopy (SERS) substrates that require nanopatterned metallic structures. It demonstrates a process for replicating a picture by a set of metallic structures that plasmonically produce the desired colors locally. It uses a digitizing computational tool, direct-write Two-Photon Lithography (TPL) and a dry-etch process to rapidly produce a silicon master. This master is used to hot emboss nano-patterns in superionic glass blanks that, in turn, are used for electrochemical imprinting with S4 to reproduce the patterns on Ag substrates. The different steps in this process flow are described along with their role and effectiveness in contributing to a high-fidelity plasmonic image reproduction.

Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

Design and analysis of an efficient low power low delay low leakage clock keeper domino logic

The design and development of CMOS VLSI semiconductor circuits employing deep sub-micron technology has faced significant challenges, primarily in terms of propagation delay and power consumption. This work introduces a new method called low leakage clock keeper domino logic (LLCKDL) for creating CMOS logic gates. The purpose of this approach is to decrease the amount of power consumed via leakage and enhance the efficiency of the gates in terms of noise. Existing and suggested methodologies can be employed to develop 16-bit input OR gates and simulated using GPDK 45 nm CMOS technological node in Cadence with a clock frequency of 10 MHz. The simulation results have been assessed by comparing the power usage, unity noise gain (UNG) and propagation latency. The Simulation outcomes show that the average power usage for the suggested domino has been improved to 87.12 %, 89.83 %, 93.38 %, 90.24 %, 86.4 %, and 88.01 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively. The delay for the suggested design has been improved to 42.66 %, 56.31 %, 29.97 %, 18.18 %, 11.25 %, and 16.95 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL, and GPKD respectively. The PDP for the suggested design has been improved to 92.62 %, 95.56 %, 95.37 %, 92.02 %, 87.94 % and 90.05 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively. The EDP for the suggested design has been improved to 95.78 %, 98.06 %, 96.76 %, 93.49 %, 89.28 % and 91.76 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively.

Variable Length and Temperature-Dependent Analysis of MLGNR at Nano-Scale Regime

In this paper, a thermally aware equivalent single conductor is proposed, along with analytical modeling to evaluate the parasitic parameters of multilayer graphene nanoribbon (MLGNR) as interconnect, and its performance is analyzed in terms of delay and power delay product (PDP) for 32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm technology nodes at variable global interconnect lengths (500–2000[Formula: see text]m). It was examined that with rising temperature, there is a strident decrease in the mean free path (MFP) of GNR interconnect, which further influences its own resistance at global length (2000[Formula: see text][Formula: see text]m) for all three technology nodes. The simulation tool Simulation Program with Integrated Circuit Emphasis (SPICE) is used to estimate and compare MLGNR performance in terms of signal delay and PDP for three different technology nodes. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (500–2000[Formula: see text][Formula: see text]m) over a temperature range of 200–500[Formula: see text]K for deep submicron technology nodes (16[Formula: see text]nm, 22[Formula: see text]nm and 32[Formula: see text]nm). A similar investigation was performed on the copper interconnect, and it was discovered that the MLGNR performs better in terms of delay and PDP at global levels with a temperature range of 200–500[Formula: see text]K for nano-scaled technology nodes (32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm).

Chiplets for Integration of Electronic Systems

Scaling down of transistor sizes has made it possible to integrate billions of devices in the same chip, allowing us to build entire electronic systems into tiny “systems on chip” (SoC). For about four decades after the proclamation of Moore's law, device scaling resulted in improvements in area, performance as well as power. In the last two decades, many semiconductor manufacturers stopped investing in new technology nodes since the design, manufacturing, and test challenges in deep submicron technologies are far too steep. Today, semiconductor companies do not rely on improvements in photolithography alone to build more complex systems. Similarly, optimizations at gate level or register-transfer level through electronic design automation tools will not suffice to bring in order-of-magnitude increase in the complexity of SoC, since these tools are already mature. Therefore, optimization at the system level is the only logical step forward. Chiplets represent a system-level packaging innovation and there is much research and development in using this technology for building high-performance computing systems. We believe that it will be worthwhile to include the topic of system-level integration in a course on Very Large-Scale Integrated Circuit Design taught in the Universities and provide a tutorial treatment to help teachers and students.

Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

The advent of device miniaturization techniques and the evolution of very deep submicron technology have led to the increased prominence of short channel effects (SCEs) in conventional transistors (CTs). Now, in the era of nanoengineering and nano-wires, current research is centered around a novel device known as the Junctionless Field Effect Transistor (JLFET), which incorporates gate-all-around engineering applications. Given the challenges associated with scaling transistor sizes, such as creating high-quality junctions and changing doping concentrations (~1019 cm–3) over a 10 nm distance, JLFET emerges as a promising alternative to CTs. Notably, JLFET lacks junctions and doping concentration gradients. In this study, the authors have conducted a comprehensive analysis and performance evaluation of JLFET and CTs, specifically in the context of low-power applications. Various performance parameters of JLFET, including SS, DIBL, transconductance, output conductance, and Ion/Ioff, have been assessed. The findings indicate that JLFET exhibits reduced susceptibility to SCEs compared to CTs and demonstrates exceptional current driving capability.

Conditional spatial transition reduction data encoding technique for VLSI interconnects

In this paper the DSM (Deep sub micron) and lower node technologies device dimensions are reduced. Compared to logic functional blocks interconnects dynamic power consumption plays most precarious factor. The most effective way to save the dynamic power in wires is to reduce the number of transitions by using the data encoder. In this paper we proposed a inverse based algorithm with mathematical proof and simple architecture. it is having the different options lower bit inversion, upper bit inversion, all bit inversions and no bit inversion, the data selection based on the which option saves the more power. It is having the simple and compact architecture and it offers less delay compared to related methods.

Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology

The Single Event Transient (SET) phenomenon, which occurs in combinational circuits, has emerged as the primary source of soft errors in Integrated Circuits (IC) in advanced deep-submicron technologies. Therefore, it is imperative to investigate the underlying mechanisms of SET effects in order to gain valuable insights for mitigating SET in combinational circuits. In advanced technologies, specifically those at the 28-nm and below, tap cells are commonly utilized as the well and substrate contact to achieve higher device density. This article presents a comprehensive study on the impact of tap cells on SET sensitivity for the first time. Furthermore, a comparison is made between the SET sensitivity of conventional and tap cell-based well and substrate contact.

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

ABSTRACT Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30–50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques are found to be 36.95% from the non-gated CORDIC LMS filter design.

Novel Second-Order Fully Differential All-Pass Filter Using CNTFETs.

In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng's CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology.

Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology

Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

<span lang="EN-US">This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (</span><span lang="EN-US">CMOS).</span>

Aspect Ratio Modeling of Radiation-Hardened 8-Shape Enclosed Layout Transistor

The leakage current caused by the total ionizing dose (TID) effect remains a challenge for deep submicron technologies. The enclosed layout transistor (ELT) NMOS using the radiation hardening by design (RHBD) technique has a great potential for TID radiation hardening. Compared with the b-shape ELT that has a clear limitation on its aspect ratio, 8-shape ELT is preferable in the circuit design. The aspect ratio modeling of 8-shape ELT is proposed in this work for the first time. The basic principle is based on the 8-shape ELT equivalent circuit, composing one main transistor and two edge transistors. In accordance with the Sentaurus simulation result, the equivalent trapezium approximation is made for the edge transistor. A semi-empirical parameter is given to calculate the proposed model. The model is verified by the comparison between measured results of the fabricated 8-shape ELT in 180nm CMOS process and the pure calculation results. A further discussion is made to improve the accuracy of the proposed model, which is approved by the comparison between different models in previous work. Some modifications are also made to adjust the 8-shape ELT before the application.

A meta-heuristic search-based input vector control approach to co-optimize NBTI effect, PBTI effect, and leakage power simultaneously

As technology advances, Bias temperature instability (BTI) has become a severe aging challenge that affects the reliability of a device. Previously, NBTI was the most significant aging issue, but with the development of the high-k metal-gate technology, the impact of PBTI can no longer be overlooked. Similarly, in deep submicron technology, leakage power also remains a serious concern. So, minimizing the consequence of the BTI effect and leakage power is the key design goal in today’s technology. As the leakage power and the BTI effects have a strong dependency on the input patterns of the circuit, the input vector control (IVC) technique can be employed to mitigate both of these effects. Previously, IVC techniques have been used to co-optimize the NBTI degradation and the leakage power. In this work, the NBTI effect, PBTI effect, and leakage power are considered simultaneously. Here, a Genetic Algorithm-based (GA) multi-objective meta-heuristic approach is proposed to select the optimum input vector for simultaneous co-optimization of NBTI effect, PBTI effect, and standby leakage power. The proposed approach shows a maximum improvement of NBTI, PBTI, and leakage power by 39.89%, 40.62%, and 37.32%, respectively, with respect to the worst-case solutions of each effect.

Time-to-digital conversion techniques: a survey of recent developments

Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for digital processing of analog signals encoded in time. Since design of time-mode circuits facilitates replacing analog blocks with digital circuitry, TDCs pave the way to hardware-efficient and purely digital architectures in deep-submicron semiconductor technology. The design and implementation of modern TDCs is heterogeneous, shaped in multiple directions, and driven by CMOS process downscaling along with application demands. The substantial research effort is made in more intensive digital implementations, optimization of techniques for high resolution, increasing input range and linearity, reduced conversion time, power consumption and silicon area. The calibration and mismatch-tolerant, as well as anti-PVT-variation and anti-metastability design techniques are of growing importance in order to alleviate imperfections of nanoscale CMOS technologies. The paper surveys recent developments of time-to-digital conversion techniques to give a possibly comprehensive picture of major trends and design advancements. Finally, we highlight TDC design challenges for cutting-edge applications such as All-Digital Phase Locked Loops for high data rate wirelesss communication systems operating in the millimeter-wave band.

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.

Radiation-tolerant all-digital clock generators for HEP applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.