Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology

Abstract

The Single Event Transient (SET) phenomenon, which occurs in combinational circuits, has emerged as the primary source of soft errors in Integrated Circuits (IC) in advanced deep-submicron technologies. Therefore, it is imperative to investigate the underlying mechanisms of SET effects in order to gain valuable insights for mitigating SET in combinational circuits. In advanced technologies, specifically those at the 28-nm and below, tap cells are commonly utilized as the well and substrate contact to achieve higher device density. This article presents a comprehensive study on the impact of tap cells on SET sensitivity for the first time. Furthermore, a comparison is made between the SET sensitivity of conventional and tap cell-based well and substrate contact.