Conditional spatial transition reduction data encoding technique for VLSI interconnects

Abstract

In this paper the DSM (Deep sub micron) and lower node technologies device dimensions are reduced. Compared to logic functional blocks interconnects dynamic power consumption plays most precarious factor. The most effective way to save the dynamic power in wires is to reduce the number of transitions by using the data encoder. In this paper we proposed a inverse based algorithm with mathematical proof and simple architecture. it is having the different options lower bit inversion, upper bit inversion, all bit inversions and no bit inversion, the data selection based on the which option saves the more power. It is having the simple and compact architecture and it offers less delay compared to related methods.