Capacitance Deep Level Transient Spectroscopy Research Articles

DLTS AS A LOCAL PROBE OF CONCENTRATION AND DEPTH OF TRAP LEVELS

Complementarity of the capacitance and charge deep level transient spectroscopy (DLTS) is the idea which led us to an advanced method for profiling trap levels in semiconductors. This unifying approach to the space-charge spectroscopy, on grounds of applying the small-amplitude-filling pulse mode and evaluating the trapped charge balance, allows one to implement it in practice while using currently available instrumentation. A simple formalism is sufficient to obtain the demanded trap level depth. The usefulness of this method is demonstrated on bulk traps found in two different metal-insulator-semiconductor (MIS) capacitors. We propose also a new experimental technique providing the option of a direct determination of the trap depth from a single temperature scan. In addition, we found an expression for the relative detection sensitivity of the capacitance DLTS and justified quantitatively the earlier reported improved relative sensitivity of the charge transient spectroscopy.

Electron paramagnetic resonance of multistable interstitial-carbon-substitutional-group-V-atom pairs in silicon.

A total of five new electron paramagnetic resonance (EPR) centers are observed in electron-irradiated P-, As-, and Sb-doped silicon. Three are identified as arising from the neutral charge state of the stable configuration and two of the four metastable configurations of an interstitial-carbon--substitutional-phosphorus (${\mathrm{C}}_{\mathit{i}}$-${\mathrm{P}}_{\mathit{s}}$) pair, recently discovered by deep level transient capacitance spectroscopy. The other two are identified as arising from the corresponding stable configurations of ${\mathrm{C}}_{\mathit{i}}$-${\mathrm{As}}_{\mathit{s}}$ and ${\mathrm{C}}_{\mathit{i}}$-${\mathrm{Sb}}_{\mathit{s}}$ pairs. Combining unusual uniaxial-stress-alignment results with analysis of the EPR spectra allows detailed models to be proposed for the different defect configurations and for the mechanism of conversion between them. We conclude that the stable state consists of a 〈100〉-split-C--group-V-atom interstitialcy which converts under electronic excitation to the metastable configurations by ejecting the carbon backward toward the nearest ${\mathit{T}}_{\mathit{d}}$ interstitial site from which it forms similar C-Si interstitialcies with its surrounding Si atoms.

Effects of particle size and shape on dimensional change during sintering: S. Masuhara, S. Kawai (Kobelco Metal Powder of America Inc, Seymour, Indiana, USA)

Electronic properties of radiation damage produced in 4H–SiC by neutron irradiation and its effect on electrical parameters of Junction Barrier Schottky (JBS) diodes were investigated. 4H–SiC N-epilayers, which formed the low-doped N-base of JBS power diodes, were irradiated with 1 MeV neutrons with fluences ranging from 1.3 × 1013 to 4.0 × 1014 cm−2. Radiation defects were then characterized by capacitance deep-level transient spectroscopy, I–V and C–V measurement. Results show that neutron irradiation introduces different point defects giving rise to acceptor levels lying 0.61/0.69, 0.88, 1.03, 1.08 and 1.55 eV below the SiC conduction band edge. Introduction rates of these centers are ranging from 0.64 to 4.0 cm−1. These defects have a negligible effect on blocking and dynamic characteristics of irradiated diodes. However, the acceptor character of introduced deep levels and their fast introduction deteriorate diode’s ON-state resistance already at fluences exceeding 1 × 1014 cm−2.

Hall effect and deep level transient spectroscopy measurements in indium selenide doped with chlorine

Abstract The temperature dependence of the Hall effect has been studied on InSe single crystals doped with Cl. The electron mobility can be explained by combining the homopolar optical-phonon and the ionized impurity scatterings. Moreover, two electron traps of depths 0.66 and 0.30 eV have been investigated by deep-level transient-capacitance spectroscopy measurements (DLTS). The first level is present in both pure and doped samples, while the second level only appears in doped samples.

Use of low-frequency capacitance in deep level transient spectroscopy measurements to reduce series resistance effects

In this article, we demonstrate the usefulness of a low-frequency capacitance deep level transient spectroscopy (LFDLTS) technique suitable for samples with a large built-in resistance in series with the depletion capacitance. As a case study, we investigate the effects of series resistance arising from the contact resistance and the bulk resistance of aluminum gallium arsenide epitaxial layers grown on semi-insulating gallium arsenide substrates. We show that there can be significant errors in the density and the activation energy of the traps (the so-called DX centers) determined by the conventional high-frequency (1 MHz) capacitance deep level transient spectroscopy measurements when the series resistance associated with the sample is high. On the other hand, the LFDLTS measurements are found to be free from these artifacts related to the series resistance effects.

Electron paramagnetic resonance of a multistable interstitial-carbon-substitutional-phosphorus pair in silicon

Two new electron paramagnetic resonance centers are reported, Si-L8 and Si-L9, which are identified with the stable and one of the four metastable configurations, respectively, of a multistable defect recently discovered by deep level transient capacitance spectroscopy in electron-irradiated phosphorus-doped silicon. Resolved 31P hyperfine interactions and stress-induced alignment effects are detected in the spectra which serve to confirm the identification as a Ci-Ps pair and lead to a model for the atomic structure in the stable configuration.

Energy and Depth Distributions of Interface States and bulk Traps and their Electronic Effects in GalnAs/GaAs Heterojuntions

ABSTRACTWe have studied the lattice-mismatch-induced defects both at the interface and in the bulk (GaAs buffer layer ) of Ga0.92In0.08As/GaAs heterojunctions by means of C-V characteristics and constant capacitance deep level transient spectroscopy (CC-DLTS). The Ga0.92In0.08As (n+)/GaAs (P) samples, with the thickness of GalnAs layer at 0.1μm, 0.25μm, 0.5μm, and 1.0μm, were grown by MBE. The depth profiles of bulk hole traps in the GaAs buffer layer were measured by the DLTS technique as a function of the in-plane lattice mismatch. The concentration of lattice-mismatch-induced traps decreased exponentially with distance away from the interface. The depth distributions of the mismatch-induced bulk traps appeared to be affected by the pre-existing bulk traps and the dopant impurities in the GaAs buffer layer. Energy distribution of the interface states was obtained by the CC-DLTS and C-V measurements independently. All heterojunctions showed a minimum in the interface state density at about EV+0.83eV. The U-shaped energy distribution with donor- and acceptor-like states is interpreted by the disorder-induced-gap-states model.

EPR identification of the single-acceptor state of interstitial carbon in silicon.

An EPR center labeled Si-L6 is reported which is identified as arising from the singly ionized acceptor state of isolated interstitial carbon (${\mathrm{C}}_{\mathit{i}}^{\mathrm{\ensuremath{-}}}$) in electron-irradiated crystalline silicon. Correlated deep-level capacitance transient spectroscopy measurements locate the acceptor level at ${\mathit{E}}_{\mathit{c}}$-0.10 eV. The core structure of the defect is a 〈100〉 C-Si interstitialcy similar to that previously proposed for ${\mathrm{C}}_{\mathit{i}}^{+}$. The spin wave function is substantially more diffuse, however.

Defects due to nonstoichiometric growth in semi-insulating GaAs and their effects on Si implantation activation efficiency

The effects of starting semi-insulating GaAs conditions on Si-implantation activation efficiency have been studied by capacitance deep level transient spectroscopy, 4.2-K photoluminescence, and thermally stimulated current spectroscopy. Experimental evidence shows that samples with good Si activation efficiency have higher EL2 trap concentration, compared with samples with a lower activation efficiency, and a higher density of trap T2 at Ev +0.49 eV believed to be the native defect AsGa++. For samples with a lower activation efficiency, a deep trap T3 attributed to either VAs or GaAs −VGa appears at Ev +0.44 eV with a concentration larger than that of T2. A PL emission at 1.44 eV due to GaAs or its related complex is observed in the samples with a lower activation efficiency, but not in samples with good activation efficiency. Comparison between samples grown under Ga-rich or As-rich conditions and samples that show different activation efficiencies confirms that growth stoichiometric conditions largely determine the Si implantation activation efficiency.

A deep-level transient spectroscopy study of high electron mobility transistors subjected to lifetime stress tests

Current and capacitance deep-level transient spectroscopy (DLTS) measurements have been used to examine the effect of accelerated lifetime stress tests on AlGaAs/GaAs high electron mobility transistor structures. The epilayers for these devices were grown by molecular beam epitaxy on semi-insulating GaAs substrates, and they were processed to have 0.7-μm long gates. The major defect detected by both the capacitance and current measurements on unstressed control devices is the DX center in the AlGaAs. The current DLTS tests on stressed samples reveal an additional defect, which is not found in capacitance DLTS measurements on the same devices. The new current DLTS line appears to be a minority-carrier trap, which is not expected as the trap filling pulse was not set to inject minority carriers. These features can be explained if the defect is associated with surface states located between the gate and either the source or the drain.

Deep-level transient spectroscopy in MOS structures with a dual-channel boxcar integrator and arbitrarily chosen gate-width–data analysis

New formulas are proposed describing the correlation signals of bulk traps and interface states in metal-oxide-semiconductor structures for constant voltage and constant capacitance deep-level transient spectroscopy analog measurement systems with a dual-channel boxcar integrator and an arbitrary gate width. An analysis presented enables one to maximize sensitivity of these systems for the study of low-concentration processing-induced defects and interface states in metal-oxide-semiconductor devices.

Deep-level admittance spectroscopy of D X centers in AlGaAs:Sn

Deep-level admittance spectroscopy (DLAS) of DX centers in AlxGa1−xAs:Sn (0.2<x<0.6) reveals the presence of three levels SN1, SN2, and SN3 related to the Sn donor. While SN1 and SN3 are observed in all the samples, SN2 is prominently seen only in the indirect band-gap samples. The conventional capacitance deep-level transient spectroscopy (DLTS) is found to be unsuitable for the study of the DX center in AlxGa1−xAs:Sn with x>0.35 because of the strong freeze-out of free carriers in these samples. Even in the case of low AlAs mole fraction samples (x<0.35), the DLTS technique fails to reveal all the levels observed by DLAS and provides information only on the SN3 level.

Alloy broadening of the emission barrier of the D X center in aluminum gallium arsenide

The effect of alloy fluctuations on the emission barrier of the DX center in aluminum gallium arsenide (AlGaAs) is studied by constant capacitance deep level transient spectroscopy using Si-doped and Sn-doped samples grown by different growth techniques. All the samples showed single broadened peaks which were analyzed by assuming a Gaussian distribution for the emission barrier. The full width at half maximum for the emission barrier spread was found to be the same (∼0.05+0.005 eV) for all the samples and is of the same order as the reported capture barrier spread for Si-doped AlGaAs, which strongly suggests that the binding energy spread of the DX center in AlGaAs is very small.

Transient Current and Transient Capacitance Measurements of Defects in AlGaAs Hemts

AbstractThe defects present in AlGaAs high electron mobility transistor (HEMT) devices subjected to accelerated lifetime tests have been studied by transient current, and when possible, by transient capacitance techniques. By measuring transient source-drain currents following the application of a voltage pulse to the gate it is possible to perform deep level transient spectros-copy (DLTS) experiments on HEMT devices which are too small for the conventional capacitance DLTS. The capacitance and current spectra for both stressed and unstressed HEMTs contain the AlGaAs DX defect. The current DLTS spectra for stressed devices contain an additional feature which is not found in capacitance DLTS measurements on the stressed HEMTs. This additional current DLTS feature is anomalous in that the transient has a sign which is opposite to that expected for a majority carrier trap. The absence of the new defect in the capacitance DLTS suggests that the defect is located in the channel between the gate and either the source or the drain. The current DLTS line shape of the stressed induced defect depends upon the polarity and size of the source-drain voltage.

Observation of a multiply charged defect in p-type CdTe

Abstract We have studied the defects in p-type CdTe after annealing under Te-vapour pressure by capacitance deep-level transient spectroscopy (DLTS). The major defect is associated with two DLTS lines with activation enthalpies of 0·20 and 0·23 eV. The ratio of their amplitudes depends on the filling pulse length and for the maximum amplitudes is two. Assuming that the defect can capture two holes, we propose a model that explains the unusual properties of this defect: the capture of the second hole is associated with a large lattice relaxation and thermally activated to such an extent that an inverted ordering of the thermal activation enthalpies is observed. From the electric field dependence of the hole emission rates we infer for one level a donor character and for the other level an acceptor character. The dependence of the defect concentration on the annealing temperature indicates that the defect is probably a Cd-vacancy complex.

Deep Level Study of VPE Layers for GaAs FET Devices

An solid source VPE system has been developed to grow device quality epi layers. The traps found by optical deep level capacitance transient spectroscopy in the epi layers grown in this system are one electron trap, identified as EL2, and three hole traps near the active layer and buffer layer interface. The hole traps were found to be impurity or intrinsic defect related. The solid source was found to be the source of impurity contamination. The intrinsic deep trap is influenced by the change in the As/Ga ratio in the gas phase. Low etch flow rate is found to minimize both the impurity transport from solid source and the intrinsic defect density.

Physical parameters of GaInAs/Si3N4 interface states obtained by the conductance method

Interface state parameters were studied in TiAu/Si3N4/Ga0.47In0.53As metal-insulator-semiconductor capacitors by conductance and capacitance measurements at various temperatures. The analysis of the data, taking into account the variation of the capture cross section versus energy, allows us to obtain the density of states, the capture cross section, the surface potential, and the dispersion parameter. The numerical values agree very well with results provided by capacitance transient methods at low temperatures (isothermal capacitance transient spectroscopy and deep level transient spectroscopy).

Generation of an anomalous hole trap in GaAs by As overpressure annealing

Deep levels in high-purity n-type molecular beam epitaxy (MBE) GaAs and in undoped n-type metalorganic chemical vapor deposition (MOCVD) GaAs samples annealed with various As overpressures were investigated using constant capacitance deep level transient spectroscopy on evaporated Au Schottky barrier diodes. Anomalous hole traps, which could be measured because of a surface effect, were observed in all annealed samples. EL2 traps were created in the MBE material by the annealing, while the concentration of EL2 in the annealed MOCVD material was about the same as that before annealing. The effect of annealing on the other electron traps in these samples is also studied and reported.

Influence of an intentional substrate misorientation on deep electron traps in AlGaAs grown by molecular beam epitaxy

Deep level transient capacitance spectroscopy has been used to investigate deep level electron traps in thick silicon-doped AlGaAs grown by molecular beam epitaxy (MBE) on GaAs substrates intentionally misoriented (tilted) a few degrees from a nominally (001) surface. Of the three dominant traps observed in AlGaAs, the concentrations of two of these are observed to be a direct function of the substrate tilt angle and tilt direction. The concentration of the third dominant trap, which is related to the DX center, is independent of substrate misorientation during MBE. These observations will help in identifying which impurities and/or defects are affected by substrate misorientation during MBE growth in addition to identifying the origin of deep levels in AlGaAs.

Capacitance spectroscopy of Si-TaSi2 eutectic composite structures

The Si matrix phase of directionally solidified Si-TaSi2 composite structures has been characterized by deep level capacitance transient spectroscopy, using the grown-in metal-semiconductor junctions. The Si is found to be of high quality. No electrically active Ta was detected with a minimum experimental sensitivity of ∼6×1011 cm−3. Some samples exhibited one of two defect states having electron emission activation energies of 0.36 and 0.65 eV. These states appear to be associated with dislocations.