Drain Current Decreases Research Articles

Drain current modulation in a nanoscale field-effect-transistor channel by single dopant implantation

We demonstrate single dopant implantation into the channel of a silicon nanoscale metal-oxide-semiconductor field-effect-transistor. This is achieved by monitoring the drain current modulation during ion irradiation. Deterministic doping is crucial for overcoming dopant number variability in present nanoscale devices and for exploiting single atom degrees of freedom. The two main ion stopping processes that induce drain current modulation are examined. We employ 500 keV He ions, in which electronic stopping is dominant, leading to discrete increases in drain current and 14 keV P dopants for which nuclear stopping is dominant leading to discrete decreases in drain current.

Fabrication Process of Carbon Nanotube Field Effect Transistors Using Atomic Layer Deposition Passivation for Biosensors

Fabrication process of the carbon nanotube (CNT) field effect transistors (FETs) for biosensors was studied. Atomic layer deposition (ALD) of HfO2 was applied to the deposition of the passivation/gate insulator film. The CNT-FETs did not show the drain current degradation after ALD passivation even though the passivation by Si3N4 deposited by plasma-enhanced chemical vapor deposition (PECVD) resulted in a significant drain current decrease. This indicates the advantage of the present ALD technique in terms of the damage suppression. The biosensing operation was confirmed using thus fabricated CNT-FETs.

Comparison of the Threshold-Voltage Stability of SiC MOSFETs with Thermally Grown and Deposited Gate Oxides

The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

Characterisation and modelling of parasitic effects and failure mechanisms in AlGaN/GaN HEMTs

This work is a study of the degradations of AlGaN/GaN HEMTs induced by 2000 h of ageing tests. The methodology is based on cross-characterisation analysis. The life tests (HTO 150 °C, HTO 175 °C and HTRB 175 °C and Idq 90 °C) have mainly induced a decrease of the saturation drain current, occurring during the first 50 h, followed by a stabilisation. There is a shift of the pinch-off voltage in the range of 0.1–0.2 V while the Schottky contact is rather stable after ageing. The evolution of the electrical characteristics after ageing does not depend on the bias conditions but rather more on the channel temperature. It seems to be neither field nor current driven. Low frequency drain current noise demonstrates that there is no trap creation and the weak evolution of the 1/ f noise confirms that there is no degradation in the channel. Moreover, pulsed I– V measurements show a weak evolution of gate lag and drain lag rates after ageing. The same degradation mode is demonstrated for all life tests with rather high activation energy of 1.6 eV. The weak evolution of electrical characteristics observed during the life tests cannot be obviously explained by a single physical mechanism and results from a combination of trap-related effects before stabilisation.

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Constant-voltage-bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 30 V) stress measurements are performed for a period of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /IGZO TFTs tested exhibit the following: 1) a positive rigid log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.

Impact of proton-radiation-induced spacer damage on the dc characteristics degradation in deep-submicron metal-oxide-semiconductor field effect transistors

The dc characteristics degradation of 0.18 μm metal-oxide-semiconductor field effect transistors (MOSFETs) after 10 MeV proton irradiation is comprehensively investigated in this paper. The measured results show that the off-state drain current is increased in N-channel MOSFETs, which is due to the turn on of the parasitic transistors induced by the shallow trench isolation regions. While in P-channel MOSFETs, the threshold voltage increase (absolute value), the transconductance degradation, and the saturation drain current decrease are observed. From the analysis, it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the isolation region. The origin of the observed changes may be mainly due to the damage in the spacer oxides of the transistors. In order to verify the assumption, the leakage current passing through the spacer between the gate and the drain is measured before and after irradiation with floated source/substrate and grounded drain. We find that the leakage current is two to three times larger after irradiation. Finally, in order to confirm the extrapolation, 2-dimension (2D) simulation has been performed with Synopsys TCAD (technical computer-aided design) Sentaurus Device Simulation tools (ISE 10.0). The behavior of the simulated charges trapped in the spacers is qualitatively consistent with the experimental results.

Progressive degradation of TiN∕SiON and TiN∕HfO2 gate stack triple gate SOI nFinFETs subjected to electrical stress

In this contribution, the authors analyze first results about the impact of electrical stress on triple gate SOI nFinFETs with metal gate (TiN) and SiON or HfO2 gate dielectrics, with particular emphasis on the roles of fin width and back gate polarization. A similar progressive degradation of the characteristics is observed for both types of gate dielectric devices. An increasing degradation with reducing fin width is observed for a certain range of wide fin devices (between about 3μm and 130nm), which could be attributed to a higher contribution of corner effects or lower quality side surfaces. However, the narrowest triple gate FinFETs with geometries around the nominal values of this technology (70nm long and 30nm wide fins) show reduced degradation with electrical stress. Under the studied experimental conditions, no clear impact on device degradation is observed for different back gate bias conditions applied during electrical stress. A typical dielectric breakdown mode characterized by a sudden decrease in drain current, accompanied by a significant increase in front gate current, is observed quite often in devices subjected to strong or long stress conditions. From the analysis of the encountered postbreakdown source/drain asymmetries, it is inferred that most of such catastrophic failures under VFG=VD stress regime may correspond to gate-to-source dielectric breakdown.

Modeling and Fabrication of ZnO Nanowire Transistors

ZnO is attracting attention for application in transparent nanowire (NW) transistors because of the ease of synthesis of ZnO nanostructures, their good transport properties, the availability of heterostructures, and the possibility for optoelectronic integration. A variety of both top and bottom gate n-type ZnO NW transistors have been reported, showing generally high on/off ratios (104 - 107), subthreshold voltage swings of 130-300 mV/dec, and excellent drain-current saturation. Much higher electron mobilities and improved device stability are found when surface passivation is employed, pointing to the importance of controlling surface charge density. Simulations show that defects such as grain boundaries lead to a decrease of drain current. While the dc characteristics of such devices are generally reasonable, there have been no reports of the RF or high-speed switching performance. Additional work is needed on optimized gate dielectrics, reliability, and functionality of ZnO NW transistors.

Radiation damage in proton-irradiated strained Si n-MOSFETs

Strained Si layers (sSi) on strain-relaxed SiGe buffer layers are frequently used in order to boost up the carrier mobility. This study investigates the degradation of such sSi n-MOSFETs by 20-MeV proton irradiation. The drain current decreases and a negative shift of the threshold voltage is observed after proton irradiation. The impact of the fabrication process of sSi transistors on the degradation is also discussed.

A reliable method for the counting and control of single ions for single-dopant controlleddevices

By 2016, transistor device size will be just 10 nm. However, a transistor that is doped at a typical concentrationof 1018 atoms cm−3 has only one dopant atom in the active channel region. Therefore, it can be predicted thatconventional doping methods such as ion implantation and thermal diffusion will not beavailable ten years from now. We have been developing a single-ion implantation (SII)method that enables us to implant dopant ions one-by-one into semiconductors until thedesired number is reached. Here we report a simple but reliable method to control thenumber of single-dopant atoms by detecting the change in drain current induced bysingle-ion implantation. The drain current decreases in a stepwise fashion as a result ofthe clusters of displaced Si atoms created by every single-ion incidence. Thisresult indicates that the single-ion detection method we have developed is capableof detecting single-ion incidence with 100% efficiency. Our method potentiallycould pave the way to future single-atom devices, including a solid-state quantumcomputer.

Anomalous Hot-Carrier-Induced Increase in Saturation-Region Drain Current in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

Anomalous increase in saturation-region drain current Id(sat) but serious on-resistance degradation (decrease in linear-region drain current) is observed in n-type high-voltage lateral diffused MOS transistors stressed under medium gate voltage Vg. However, Id(sat) is degraded for the devices stressed under low and high Vg. Experimental data reveal that two competing mechanisms are responsible for the shift of Id(sat). One is the interface state Nit formation in the N- drift region. The other is the Nit formation in the channel region. The former mechanism leads to the anomalous increase in Id(sat), whereas the latter mechanism causes the to decrease. Experimental data and technology computer-aided-design simulations confirm that the impact ionization rate of the device is enhanced if significant Nit formation in the N- drift region is present. According to the results presented in this paper, significant formation in the drift region is identified to be the main mechanism responsible for the anomalous increase in Id(sat).

Quantum cascade multi-electron injection into Si-quantum-dot floating gates embedded in SiO 2 matrices

The use of silicon-quantum-dots (Si-QDs) as floating gates in metal-oxide-semiconductor-field-effect-transistors (MOSFETs) has been attracting great attention. It has been reported that large decreases in drain current are observed within a very short time in Si-QDs memories, indicating that the collective motion of electrons occurs during electron injection into Si-QDs. In this study, we present a theoretical report which indicates that the interaction length between QDs is about 5–10 nm. From these results, we propose a mechanism for “quantum cascade multi-electron injection”.

Degradation Mechanism of AlGaAs/InGaAs Power Pseudomorphic High-Electron-Mobility Transistors under Large-Signal Operation

We have comprehensively investigated the degradation mechanism of output power in AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (PHEMTs) under large-signal operation. The degradation of output power is caused by the decrease in maximum drain current (Imax) around the knee voltage (Vk) with an increase in drain resistance (Rd). The decrease in Imax originates from a degradation layer containing a significant amount of oxygen formed at the drain recess surface region. This layer causes a reduced carrier density in the drain region underneath, resulting in a decreased Imax and an increased Rd. The decrease in Imax is accelerated with increasing drain voltage, temperature, and humidity. These results suggest that the degradation of output power in the PHEMTs is mainly determined by the growth of a corrosion layer owing to an electrochemical reaction between O2 and/or H2O and the semiconductor surface. We successfully suppress the output power degradation due to this electrochemical corrosion reaction with the help of a special surface treatment prior to the deposition of a passivation film on the recess surface. We demonstrate a highly reliable RF operation of PHEMTs in air even without a hermetic package.

Extraction of the Threshold-Voltage Shift by the Single-Pulse Technique

Methods for extracting threshold-voltage shift (DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) in high-kappa transistors using the single-pulse drain current-gate voltage (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) technique were compared with respect to their accuracies and limitations. It is concluded that an accurate estimation of the (DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) caused by charge trapping in high-kappa dielectrics can be obtained from the hysteresis of the pulsed (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) curve with proper calibration of the pulse measurement to account for the propagation delay. The (DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) extraction that is based on the decrease of drain current during a pulse tends to underestimate charge trapping for higher pulse amplitudes.

A Substrate Bias Effect on Recovery of the Threshold Voltage Shift of Amorphous Silicon Thin-Film Transistors

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated on a flexible stainless-steel (SS) substrate. The stability of the a-Si:H TFT is a key issue for active matrix organic light-emitting diodes (AMOLEDs). The drain current decreases because of the threshold voltage shift (ΔVTH) during OLED driving. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and the gate electrode without additional circuits. The negative voltage biased at the SS substrate can recover ΔVTH and reduced drain current of the driving TFT. The VTH of the TFT increased by 2.3 V under a gate bias of +15 V and a drain bias of +15 V at 65 °C applied for 3,500 s. The VTH decreased by -2.3 V and the drain current recovered 97% of its initial value under a substrate bias of -23 V at 65 °C applied for 3,500 s.

Hot-carrier degradation for 90 nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90 nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide under the low gate voltage (LGV) (at Vg = Vth, where Vth is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (Vg = Vth) stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Vg = Vth with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (~0.8).

Impact of Heavy-Ion Strikes on Nanocrystal Non Volatile Memory Cell Arrays

In this work we focused our attention on heavy ion irradiation effects on nanocrystal memory cell arrays. All cells are fabricated by depositing Si nanocrystal on top of a SiO2 layer. Immediately after irradiation we observed neither charge loss following the ion hit, nor appreciable change of the electrical characteristics of the nanocrystal MOSFETs, such as transconductance and drain current decrease. In addition, despite the gate oxide leakage current may show a large increase after irradiation with high energy ions, the data retention time of the cells is not compromised, due to the discrete nature of the nanocrystal storage node

Peptide−Nucleic Acid-Modified Ion-Sensitive Field-Effect Transistor-Based Biosensor for Direct Detection of DNA Hybridization

Here, we report the development of a peptide-nucleic acid (PNA)-modified ion-sensitive field-effect transistor (IS-FET)-based biosensor that takes advantage of the change in the surface potential upon hybridization of a negatively charged DNA. PNA was immobilized on a silicon nitride gate insulator by an addition reaction between a maleimide group introduced on the gate surface, the succinimide group of N-(6-maleimidocaproyloxy) succinimide, and the thiol group of the terminal cysteine in PNA. The surface was characterized after each step of the reaction by X-ray photoelectron spectroscopy analysis, and the kinetic analysis of the hybridization events was assessed by surface plasmon resonance. In addition, we measured the -potential before and after PNA-DNA hybridization in the presence of counterions to investigate the change in surface charge density at the surface-solution interface within the order of the Debye length. On the basis of the zeta-potential, the surface charge density, DeltaQ, calculated using the Grahame equation was approximately 4.0 x 10(-3) C/m2 and the estimated number of hybridized molecules was at least 1.7 x 10(11)/cm2. The I-V characteristics revealed that the PNA-DNA duplexes induce a positive shift in the threshold voltage, VT, and a decrease in the saturated drain current, ID. These results demonstrate that direct detection of DNA hybridization should be possible using a PNA-modified IS-FET-based biosensor. PNA is particularly advantageous for this system because it enables highly specific and selective binding at low ionic strength.

Enhancement of drain current density by inserting 3nm Al layer in the gate of AlGaN∕GaN high-electron-mobility transistors on 4in. silicon

Al Ga N ∕ Ga N high-electron-mobility transistors (HEMTs) on 4in. Si were fabricated by inserting 3nm of Al metal as a gate prior to the deposition of Pd∕Ti∕Au. The increase of drain current (IDSmax) density and decrease of extrinsic transconductance (gmmax) have been observed in the Al-gated AlGaN∕GaN HEMTs. The increase of IDmax is due to the increase of two-dimensional electron gas sheet carrier density, which was confirmed by capacitance-voltage (C-V) measurements. Moreover, the Al layer inserted-gate HEMT exhibited negative threshold voltage (Vth) shift. The Al and AlGaN interface shows Al-based oxide layer which was confirmed by Auger electron spectrum and x-ray photoelectron spectrum.

Correlating gate sinking and electrical performance of pseudomorphic high electron mobility transistors

Ti interdiffusion from the Ti/Pt/Au gate into the AlGaAs Schottky barrier layer (SBL) of 0.25-μm GaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) has been studied using the accelerated life testing technique. Based on measurements and modeling, analytical expressions for quantitative correlation between the positive pinch-off voltage ( V P) shift as well as the saturation drain current ( I Dsat) decrease and the physical damage occurring during gate sinking has been developed. It is suggested that the main cause for device failure is the growth of the TiAs phase leading to the decrease in the SBL thickness. Additionally, it is suggested that V P may be used as a better indicator for device degradation than I Dsat since it is linearly proportional to the degrading physical characteristic – the Schottky barrier layer thickness.