Modeling and Fabrication of ZnO Nanowire Transistors

Abstract

ZnO is attracting attention for application in transparent nanowire (NW) transistors because of the ease of synthesis of ZnO nanostructures, their good transport properties, the availability of heterostructures, and the possibility for optoelectronic integration. A variety of both top and bottom gate n-type ZnO NW transistors have been reported, showing generally high on/off ratios (104 - 107), subthreshold voltage swings of 130-300 mV/dec, and excellent drain-current saturation. Much higher electron mobilities and improved device stability are found when surface passivation is employed, pointing to the importance of controlling surface charge density. Simulations show that defects such as grain boundaries lead to a decrease of drain current. While the dc characteristics of such devices are generally reasonable, there have been no reports of the RF or high-speed switching performance. Additional work is needed on optimized gate dielectrics, reliability, and functionality of ZnO NW transistors.