Drain Current Decreases Research Articles

Label-Free Electrochemical Sensor Sensitivity Enhancement Using Field Effect Transistors: Fluoride Ions for Fuel Cell Degradation Analysis

In the context of proton exchange membrane fuel cells, precise monitoring of fluoride ions in the effluent water is crucial. Associated with the fluoride ion accumulation, membrane degradation and reduction of fuel cell efficiency arise. This study focuses on developing extended gate field-effect transistors (EGFET) sensors for real-time monitoring of fluoride ion concentrations. High sensitivity and specificity in detecting the concentration of fluoride ions using both N-type (TN0702) and P-type (LP0701) metal-oxide-semiconductor field-effect transistors (MOSFET) were achieved. The transfer characteristics (Id vs Vgs) owere thoroughly examined across a range of fluoride concentrations from parts per million (ppm) to parts per billion (ppb). N-type MOSFET-based sensors showed a distinct decrease in drain current (Id) with increasing fluoride concentration. With fluoride concentrations changed, the P-type MOSFET exhibited a notable shift in the threshold voltage (Vgs). A robust linear relationship was observed on calibration curves with R2 values exceeding 0.90 between the natural logarithm of fluoride concentration (lnC) and gate-source voltage (Vgs). This work demonstrates that MOSFET can significantly enhance the sensitivity of electrochemical sensors without complex labeling processes. The improvement has a future in the miniaturization of cost-effective sensor systems for fuel cell applications, facilitating real-time performance and degradation monitoring.

Improvement of Single Event Transient Effects for a Novel AlGaN/GaN High Electron-Mobility Transistor with a P-GaN Buried Layer and a Locally Doped Barrier Layer.

In this paper, a novel AlGaN/GaN HEMT structure with a P-GaN buried layer in the buffer layer and a locally doped barrier layer under the gate (PN-HEMT) is proposed to enhance its resistance to single event transient (SET) effects while also overcoming the degradation of other characteristics. The device operation mechanism and characteristics are investigated by TCAD simulation. The results show that the peak electric field and impact ionization at the gate edges are reduced in the PN-HEMT due to the introduced P-GaN buried layer in the buffer layer. This leads to a decrease in the peak drain current (Ipeak) induced by the SET effect and an improvement in the breakdown voltage (BV). Additionally, the locally doped barrier layer provides extra electrons to the channel, resulting in higher saturated drain current (ID,sat) and maximum transconductance (gmax). The Ipeak of the PN-HEMT (1.37 A/mm) is 71.8% lower than that of the conventional AlGaN/GaN HEMT (C-HEMT) (4.85 A/mm) at 0.6 pC/µm. Simultaneously, ID,sat and BV are increased by 21.2% and 63.9%, respectively. Therefore, the PN-HEMT enhances the hardened SET effect of the device without sacrificing other key characteristics of the AlGaN/GaN HEMT.

Investigating the effect of O2 plasma treatment on the operational characteristics of Schottky-gate AlGaN/GaN HEMT

This study investigates the effect of O2 plasma treatment on the physical and electrical properties of the surface region in Schottky-gate AlGaN/GaN high electron mobility transistor (HEMT). We demonstrate that O2 plasma treatment significantly reduces the gate leakage current and enhances the on/off ratio by three orders of magnitude compared to devices without treatment. The O2 plasma treatment removes organic chemical residue and forms Ga–O bonds on the AlGaN surface beneath the gate metal. X-ray photoelectron spectroscopy results indicate that the treatment effectively forms a Ga–O compound oxide layer, which provides surface passivation. Furthermore, atomic force microscope analysis reveals a 50% reduction in surface roughness after the O2 plasma treatment. Using O2 plasma oxidation treatment caused a shift in the threshold voltage (VTH ) of Schottky-gate AlGaN/GaN HEMT. Initially measured at −5.26 V, the VTH value shifted to +0.5 V. Furthermore, we also employ TCAD simulation to assist in the process developed during the manufacturing process. It is worth noting that the drain current decreases as the Ga–O compound oxide layer increases. This is due to effectively depleted the polarization charges at the AlGaN/GaN interfaces during E-mode operation when reducing the thickness of the AlGaN layer beneath the gate metal. Our results demonstrate the importance of O2 plasma surface treatment in achieving optimal device performance. This study systematically discusses the effect of O2 plasma on AlGaN/GaN surface properties and the formation of Ga–O bonding. It offers insights into developing high-performance Schottky-gate AlGaN/GaN HEMT.

Characterization of trap evolution in GaN-based HEMTs under pulsed stress

In this paper, the evolution of traps in GaN-based high-electron-mobility transistors under pulsed thermal stress and the combined effect of thermal stress and electrical stress are studied. By applying impulse stresses of different powers to the device, collecting transient current response curves, and accurately extracting the time constant and absolute peak changes of the traps by employing the Bayesian inverse convolution theory time constant spectral technique, we analyzed the evolution of the traps under the action of impulse stress and clarified the influence and degradation mechanism of the thermal stress, as well as the combined action of thermal stress and electrical stress, on the evolution of traps. The results show that under pulsed stress, the decrease in electron mobility with increasing temperature leads to a decrease in device drain current, and the degradation of the device is exacerbated owing to channel hot-electron injection.

Electrical Characteristics of Single Layer Graphene Ribbons in a Wide Temperature Range

This paper provides electrical characterization of single layer graphene ribbon devices defined as back-gated graphene transistors. The two-terminal back-gated graphene ribbon devices were fabricated on a conventional Si substrate covered by a 90 nm-thick thermal SiO2. The chemical vapor deposition process was used for the graphene layer deposition and its quality was checked with optical microscopy, scanning electron microscopy and Raman spectroscopy. For the device fabrication, optical lithography was used for electrode patterns through a mask, and Ti/Au (10 nm/100 nm) metallic contacts were deposited by thermal evaporation. We report low and high field electrical measurements of several devices, under a controlled environment over a wide temperature range, from 77 to 300 K. At 77 K, the drain current decreases, i.e. the resistance of the graphene increases, and the nonlinearity is still present. The maximum influence of the temperature is reached at the charges neutrality point, and we observe that the temperature could influence the position of the charge neutrality point. This indicates that the carriers are thermally activated, which yields a least pronounced current with the increase of the back gate voltage.

Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors

—In this paper, the gate/drain voltage-dependent self-heating effect (SHE) in gate-all-around (GAA) nanosheet field effect transistors (NSFETs) and FinFETs is investigated by 3-D TCAD simulation. The drain current decreases because of the SHE and is dependent on the gate/drain voltage in different devices. Furthermore, the lattice maximum temperature-rise (ΔTmax), which directly leads to current degradation due to stronger carrier mobility scattering under higher temperature, exhibits complex trends with increased gate/drain voltages. The ΔTmax increases at a decreasing rate with increasing VGS but increases approximately linearly as VDS increases. To investigate the origin of these behaviors, changes in thermal resistance (Rth) due to the shift in hot spot location and the redistribution of heat source under different applied voltages are also examined. The Rth decreases as VGS increases and slightly increases at a larger VDS. The Rth of NSFETs is generally larger than that of FinFETs, and the narrow-width NSFET (N-NSFET) has the largest Rth owing to the GAA structure and narrower sub-fin structure. Additionally, the heat flux ratio of the source thermal contact in N-NSFETs is smaller than that in FinFETs for different gate and sub-fin structures, resulting in reduced mean ΔT (ΔTmean) of N-NSFETs under a larger VGS, and therefore, leading to less current degradation. The study provides one effective design guide for GAA NSFETs optimizing their thermal characteristics in advanced nodes.

Improvement of single event effects in InP-based HEMT with a composite channel of InGaAs/InAs/InGaAs

In this paper, a hardened single event effects in InP-based HEMT with a InGaAs/InAs/InGaAs composite channel (CC HEMT) is investigated by the two-dimensional numerical simulations. The composite channel significantly improves the single event effects. Compared to the conventional InP-based HEMT with single InGaAs channel (SC HEMT), the peak drain current is markedly decreased for CC HEMT, owing to a high barrier in the InGaAs/InAs/InGaAs locates electrons in the middle of the sandwiched layer. In addition, the electron concentration of the InAs channel is smaller of CC HEMT than that of InGaAs channel of SC HEMT after ion strike. This also makes the decrease in drain current. Through optimal device parameters, the peak drain current of the CC HEMT with 9/1/5 nm In0.8Ga0.2As/InAs/In0.8Ga0.2 channel is 129.1 % smaller than that of the SC HEMT with In0.53Ga0.47 channel.

Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters

A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively.
 HIGHLIGHTS
 
 Comparative study of Double Gate and Silicon on Insulator MOSFET
 Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org
 Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes
 Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET
 Contour plot for electron concentration and potential
 
 GRAPHICAL ABSTRACT

Carbon monoxide detection down to ppb-level realized by O2 plasma treated TiO2-gated AlGaN/GaN HEMT sensor

The AlGaN/GaN high electron mobility transistor (HEMT) based sensors with O2 plasma treated TiO2 film as the gate electrode were fabricated. The ultrafast ppb-level carbon monoxide detection was achieved under dry air atmosphere. It is revealed that the O2 plasma treatment on TiO2 film significantly increases the effective work function of TiO2 film due to the strong dipole layer formation which is induced by the adsorption of O2 bonding states. As a result, the HEMT drain current observably decreases. Thus, when CO gas is introduced, the reduction reaction between O2 bonding states and CO molecules weakens the strength of the formed dipole layer, resulting in the decrease of the effective work function of TiO2 electrode and the significant increase of HEMT conduction current. It is demonstrated that with O2 plasma treatment the gas sensor based on TiO2 gated AlGaN/GaN HEMT can detect CO concentration down to 10 ppb with a response time of ~100 s and 0.15 mA conduction current variation. Furthermore, the ultrafast response time of ~4 s for ≥ 500 ppb CO, high resolution of CO concentration, and long-term stability are also demonstrated.

Stability of wireless power transfer using gamma-ray irradiated GaN power HEMTs

In this work, we have demonstrated the wireless power transfer (WPT) system based on the pristine and irradiated E-mode GaN devices. The GaN device has been irradiated up to the 100 kGy dose under the γ-ray irradiation, showing the improved electrical characteristic, such as the drain current increase (~8.34%) and gate current decrease (~−7.79%). An off-state drain induced instability measurement shows the robust performance in pristine and irradiated GaN device. Noted that the irradiated device exhibits less ΔVTH, suggesting the device instability has been improved. Moreover, the wireless power transfer efficiency was evaluated by utilizing different load (20 Ω ~ 120 Ω) at VDS = 50 V and VGS = 4 V. The results indicate that the transfer efficiency of WPT by implementing the pristine and irradiated GaN device are similar. Furthermore, the output power of WPT using the irradiated GaN device becomes higher, which is mainly due to the improved drain current in irradiated GaN power devices.

Drain Field Plate Impact on the Hard-Switching Performance of AlGaN/GaN HEMTs

In this work, an analysis of the impact of drain field plate (FP) length on the semi- ON degradation of AlGaN/GaN high-electron-mobility transistors (HEMTs) is performed. A wafer-level characterization, by means of pulsed stress tests, reveals a faster and more severe decrease of the drain current in the linear region for the samples with longer drain FP. 2-D technology computer-aided design (TCAD) hydrodynamic simulations show that a time and field-dependent hot electrons (HEs) trapping takes place at the passivation/barrier interface. The higher drain current decrease in the longer FP samples can be ascribed to an enhanced HE trapping at the drain FP edge due to a different electric field distribution.

Low temperature multi-differential operational amplifier

A multi-differential operational amplifier, called OAmp3, designed for operation at temperatures up to minus 197 °С and developed on bipolar transistors and junction field-effect transistors of the master slice array МН2ХА030, is considered in the article. The circuitry features of the OAmp3 allow, due to the use of various negative feedback circuits, to implement a set of functions necessary for signal processing on a single amplifier: amplification (or current – voltage conversion), filtering, shift of the constant output voltage level. The performed measurements of OAmp3, connected as instrumentation amplifier circuit, showed that all manufactured products retain their performance in the temperature range from minus 150 °С to 20 °С, and individual samples – at minus 197 °С. It was found that the main reason for the loss of OAmp3 performance is an increase of the resistance of semiconductor resistors by almost 5.4 times at minus 197 °С compared to normal conditions and decrease in the junction field-effect transistor drain current. Together, these factors lead to decrease in the current consumption of the OAmp3 by almost 31 times at minus 180 °С compared to normal conditions. To reduce the temperature dependence of the current consumption and, thus, save the OAmp3 operability at low temperatures without changing the technological route of integrated circuits manufacturing, it is proposed to replace high-resistance semiconductor resistors with “pinch-resistors” formed on a small-signal p-junction field-effect transistor. The article presents the OAmp3 connection circuit in the form of an instrumental amplifier, the method and results of low-temperature measurements of experimental samples.

Design of Ga2O3 modulation doped field effect transistors

The design of β-Ga2O3-based modulation-doped field effect transistors is discussed with a focus on the role of self-heating and resultant modification of the electron mobility profile. Temperature- and doping-dependent model of the electron mobility as well as temperature- and orientation-dependent approximations of the thermal conductivity of β-Ga2O3 are presented. A decrease in drain current was attributed to a position-dependent mobility reduction caused by a coupled self-heating mechanism and a high electric-field mobility reduction mechanism. A simple thermal management solution is presented where heat is extracted through the source contact metal. Additionally, it is shown that an undesired secondary channel can form at the modulation-doped layer that is distinguished by an inflection in the transconductance curve.

Comparative Investigation of AlGaN/AlN/GaN High Electron Mobility Transistors with Pd/GaN and Pd/Al2O3/GaN Gate Structures

In this article, the electrical characteristics of Al0.28Ga0.72 N/AlN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with a 20-nm-thick Al2O3 layer by using radio-frequency sputtering as the gate dielectric layer are compared to the conventional metal-semiconductor HEMT (MS-HEMT) with Pd/GaN gate structure. For the insertion of the Al2O3 layer, the energy band near the AlN/GaN heterojunction is lifted slightly up and the 2DEG at the heterojunction is reduced to shift the threshold voltage to the right side. Experimental results exhibits that though the maximum drain current decreases about 6.5%, the maximum transconductance increases of 9%, and the gate leakage current significantly reduces about five orders of magnitude for the MOS-HEMT than the MS-HEMT.

Charge-Plasma Based Cylindrical Nanowire FET for Low-Noise and High Sensing

A dopingless Cylindrical Nanowire Field Effect Transistor is proposed by implementing the charge plasma technique. The charge plasma technique helped in the necessary doping of the source/drain regions. The significance of using charge plasma based Nanowire FET for low-noise and higher sensing applications is investigated by analyzing the linearity parameters and compared with the Junctionless Nanowire FET. The proposed device is optimized as per the practical conditions by taking the interface trap charges into account. The interface trap charges are considered at the gate oxide-channel interface. The variation of interface trap charge (ITCs) density varies the device performance depending on the ITC polarity. The presence of ITCs can enhance device performance by tweaking the ITCs amplitude with positive polarity. The work function of the source/drain metal for the charge plasma technique is varied to get an optimized value. The higher value of source/drain metal degrades the device performance. The voltage interception point of the proposed device is greater than 5 times the actual value of the input signal. The drain current decreases drastically with the increase of source/drain work function independent of the gate bias.

Long‐Term Retention of Low‐Power, Nonvolatile Organic Transistor Memory Based on Ultrathin, Trilayered Dielectric Containing Charge Trapping Functionality

AbstractA new strategy for multilayer stacking using charge trapping layer (CTL) is proposed and a new CTL material is synthesized, which contains a trilayer dielectric with the total thickness less than 28 nm, deposited by initiated chemical vapor deposition (iCVD) process. 2.6 nm thick poly(1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) and 19 nm thick poly(1,4‐butanediol diacrylate) (pBDDA) are employed as tunneling and blocking dielectric layers, respectively. A 6 nm thick ultrathin charge trapping layer containing hydroxyl group is inserted between the tunneling and the blocking layers for stable, long‐term memory operation. For this purpose, a homogeneous copolymer of 1,4‐butanediol diacrylate and 2‐hydroxyethyl acrylate is newly synthesized. The fabricated memory with the trilayer dielectric shows larger than 5.8 V of memory window at low programming/erasing voltage of 16 V. The retention characteristics of the low‐power organic memory device is improved significantly with the drain current decrease less than 0.40 order after 108 s, corresponding to one of the longest retention time periods obtained from organic NVM reported to date. The low‐power organic NVM could also be integrated on flexible substrate, which is fully operational even under 2.72% of applied strain.

Effect of quantum confinement on the defect-induced localized levels in 4H-SiC(0001)/SiO2 systems

In the present study, we characterize the nature of interface states in silicon carbide (SiC) metal–oxide–semiconductor (MOS) systems by analyzing the electrical characteristics of MOS field effect transistors (MOSFETs) based on the results of numerical calculations. In the calculation, the potential distributions and energy sub-bands were calculated by solving Poisson and Schrödinger equations, respectively. As a result, we demonstrate that the defect-induced localized levels in the bandgap are subjected to quantum confinement at the inversion layer, leading to the increase in their energy levels. The result implies that the conventional interface defects (e.g., near-interface oxide traps), which create defect states at certain energy levels measured from the vacuum level, are unlikely to be the major origin of the interface states in SiC MOS systems. The interface state density is almost uniquely determined by the oxide formation process (as oxidation or interface nitridation) and independent of the acceptor concentration (3 × 1015–1 × 1018 cm−3). It is also suggested that the drain current decrease observed in heavily doped MOSFETs is mainly due to the decrease in the drift mobility rather than that in the free carrier density.

A novel SOI MESFET to spread the potential contours towards the drain

ABSTRACT This paper presents a new structure of Metal Semiconductor Field Effect Transistor (MESFET) for high power applications. One of the problems that we face in the design of the MESFET devices is that in most cases, the increase of breakdown voltage is accompanied by a decrease in the saturation drain current. Our aim to propose this structure is to improve these two parameters simultaneously. Using the insulator region under the sides of the gate (IR) and the hide field plate (HFP) in the buried oxide (BOX) are the fundamental solution for improving these parameters. We named the proposed structure as spread potential contours towards the drain MESFET (SPC-MESFET). By applying the proposed structure, the drain current and the breakdown voltage improve 20 and 27 percent compared to a conventional structure (C-MESFET), respectively. Therefore, the proposed device has a higher maximum power density than the C-MESFET structure. Also, this idea reduces the gate capacitance and thus the frequency characteristics such as cut off frequency (fT), maximum oscillation frequency (fmax), and Maximum Available Gain (MAG) improve in comparison with the C-MESFET structure.

High‐Temperature Operation of AlxGa1−xN (x > 0.4) Channel Metal Oxide Semiconductor Heterostructure Field Effect Transistors with High‐k Atomic Layer Deposited Gate Oxides

Due to their superior breakdown fields compared with GaN and SiC and high thermal conductivity, AlxGa1−xN (x > 0.4) channel high‐electron‐mobility transistors (HEMTs) will find applications in extreme environments such as power electronics. Herein, the high‐temperature operation of ultrawide‐bandgap (UWBG) Al0.65Ga0.35N/Al0.4Ga0.6N metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) with atomic layer‐deposited (ALD) high‐k gate dielectrics TiO2, Al2O3, and ZrO2 is reported. As compared with similar geometry HFETs, these devices exhibit a simultaneous reduction in gate‐leakage current by ≈104 and a positive shift of the threshold voltage as much as 4 V. This positive threshold shift indicates the introduction of negative charges at the oxide/barrier interface and within the thin oxide, attributed to the pre‐ALD plasma treatment. The gate leakage increases weakly with temperature up to 250 °C, whereas the peak drain currents decrease from ≈0.5 to 0.3 A mm−1. An analysis of the C–V and I–V characteristics reveals that this drain current decrease is due to a reduction in channel electron mobility. The potential mechanisms responsible for this are discussed. Up to the measured temperature of 250 °C, the devices withstand repeated temperature cycles without catastrophic degradation or breakdown, underscoring the promise of these materials.

Neutron-induced displacement damage effect and mechanism of AlGaN/GaN high electron mobility transistor

In this paper, neutron-induced displacement damage effects of AlGaN/GaN High electron mobility ransistor (HEMT) device and heterostructure on the Xi’an pulse reactor are studied. The equivalent 1 MeV neutron fluence is 1 × 10<sup>14</sup> n/cm<sup>2</sup>. The direct-current characteristics and low frequency noise characteristics of the HEMT deviceare used to characterize the performances before and after being irradiated by the neutrons, and then the experimental results are analyzed theoretically. The analysis results showed that the displacement damage effect caused by the neutron irradiation will introduce the bulk defects into the device. The bulk defects at the channel cause the electrical performance of the device to degrade through trapping electrons and scattering electrons, which are mainly manifested as the drift of positive threshold voltage, the decrease of output saturation drain current, and the increase of gate leakage current. In order to further confirm the effect of neutron irradiation on the defect density of the device, we implement the low-frequency noise test and the calculation of the device, and the results show that the defect density at the channel of the device increases from 1.78 × 10<sup>12</sup> cm<sup>–3</sup>·eV<sup>–1</sup> to 1.66 × 10<sup>14</sup> cm<sup>–3</sup>·eV<sup>–1</sup>, which is consistent with the results of the electrical characteristics test, indicating that the new defects introduced by neutron irradiation do degrade the electrical performance of the device. At the same time, the capacitor-voltage test is also carried out to analyze the Schottky heterojunctions before and after neutron irradiation. It is found that the channel carrier concentration is significantly reduced after irradiation, and the flat band voltage also drifts positively. The analysis shows that after irradiating the device with neutrons, a large number of defects will be generated in the channel, and these defects will affect the concentration and mobility of the channel carriers, which in turn will influence the electrical performance of the device. These experimental results can be used for designing the AlGaN/GaN high electron mobility transistor for radiationhard reinforcement.