Decoding Of Low-density Parity-check Codes Research Articles

Effect of Random Jitter on Performance of LDPC

Low density parity check codes (LDPC) by now is an excellent channel code that approaches Shannons limit. In order to get the effect of random jitter on performance of LDPC, a simulation model is constructed in this paper. Interpolation, filter delay and decimation methods are used to simulate random jitter induced by circuits of the receiver, changing filter delay to control the jitter step length. Thus the bit error rate of LDPC decoder is gotten that shows the sensitivity of LDPC to synchronization jitter. This paper concludes that, complying with channel coding block in DVB-S2, the bit error rate of LDPC decoder goes up on an exponential trend with the effect of random jitter simulation.

Performance enhancement of power line communication systems with efficient low density parity-check codes, noise removal, equalization, and chaotic interleaving

Power Line Communication (PLC) offers a convenient and inexpensive medium for high-speed data transmission; however, this technology still faces difficult challenges. In particular, the Power Line (PL) channel suffers from multipath propagation accompanied with frequency-selective fading. This paper presents a method for constructing Low Density Parity-Check (LDPC) codes for Forward Error-Correction (FEC) on PL channel combined with Chaotic Interleaving (CI) and linear equalization to compensate for burst errors and multipath effects. First, the PL channel characteristics are introduced. A new way of noise modeling, which takes into account both background and impulse noises, is presented. Unlike Middletonʼs class A noise model, the proposed model is suitable for PLC channel. Noise bursts last no longer than 0.1 ms and they are characterized by Poisson distribution with an impulse arrival rate of 0⩽λ⩽5×10−3. In addition, we present a new algorithm for detection and removal of the impulse noise, by which a gain of 1.5 dB could be obtained. Concerning the system design, Zimmermannʼs model for PLC channel is considered, and then the proposed LDPC code construction method is presented. A Modified Shortest-Path (MSP) algorithm of low complexity is applied to obtain a code graph of the desired structure. The parity-check matrix of the code is constructed column-by-column subject to bit-degree and girth constraints. Both high rate and high girth codes have been constructed, e.g., code rates of 0.94, 0.95, 0.96, and 0.97. For better decoding of LDPC codes, an accurate estimation of Signal-to-Noise Ratio (SNR) is required. Therefore, we introduce a new method for SNR estimation based on higher-order signal statistics. The proposed method is especially beneficial at low SNRs. Furthermore, to achieve better immunity to burst and impulse noise, a novel interleaving scheme based on chaotic Baker map is proposed. Eventually, transmission of images on PL channel has been carried out using computer simulations. Clear images were reconstructed and the proposed algorithms were shown to perform well over PLC channel.

Study on a New Joint Source-Channel Decoder Design

To improve upon the Low-Density Parity-Check (LDPC) codes , incorporating compressed sensing (CS) and information redundancy, a new joint decoding algorithm frame is presented. The proposed system exploits the information redundancy by CS reconstruction during the iterative decoding process to correct decoding of LDPC codes. The simulation results show that the algorithm presented can improve system decoding performance and obviously make bit error ratio (BER) lower then traditional LDPC codes. In addition, a relatively short argument is given on different CS reconstructed algorithms in proposed system, the new design is shown to benefit from different CS reconstructed algorithms.

PMD mitigation through interleaving LDPC codes with polarization scramblers

The combination of forward error correction (FEC) and distributed fast polarization scramblers (D-FPSs) is approved an effective method to mitigate polarization mode dispersion (PMD) in high-speed optical fiber communication system. The low-density parity-check (LDPC) codes are newly introduced into the PMD mitigation scheme with D-FPSs in this article as one of the promising FEC codes to achieve better performance. The scrambling speed of FPS for LDPC (2040, 1903) codes system is discussed, and the reasonable speed 10MHz is obtained from the simulation results. For easy application in practical large scale integrated (LSI) circuit, the number of iterations in decoding LDPC codes is also investigated. The PMD tolerance and cut-off optical signal-to-noise ratio (OSNR) of LDPC codes are compared with Reed–Solomon (RS) codes in different conditions. In the simulation, the interleaving LDPC codes bring incremental performance of error correction, and the PMD tolerance is 10ps at OSNR=11.4dB. The results show the meaning of the work is that LDPC codes are a substitute for traditional RS codes with D-FPSs and all of the executable code files are open for researchers who have practical LSI platform for PMD mitigation.

A fast LDPC encoder/decoder for small/medium codes

Although Low-Density Parity-Check (LDPC) codes perform admirably for large block sizes — being mostly resilient to low levels of channel SNR and errors in channel equalization — real time operation and low computational effort require small and medium sized codes, which tend to be affected by these two factors. For these small to medium codes, a method for designing efficient regular codes is presented and a new technique for reducing the dependency of correct channel equalization, without much change in the inner workings or architecture of existing LDPC decoders is proposed. This goal is achieved by an improved intrinsic Log-Likelihood Ratio (LLR) estimator in the LDPC decoder — the ILE-Decoder, which only uses LDPC decoder-side information gathered during standard LDPC decoding. This information is used to improve the channel parameters estimation, thus improving the reliability of the code correction, while reducing the number of required iterations for a successful decoding. Methods for fast encoding and decoding of LDPC codes are presented, highlighting the importance of assuring low encoding/decoding latency with maintaining high throughput. The assumptions and rules that govern the estimation process via subcarrier corrected-bit accounting are presented, and the Bayesian inference estimation process is detailed. This scheme is suitable for application to multicarrier communications, such as OFDM. Simulation results in a PLC-like environment that confirm the good performance of the proposed LDPC coder/decoder are presented.

Check Node Reliability-Based Scheduling for BP Decoding of Non-Binary LDPC Codes

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation

This paper studies the feasibility and potential of using planar embedded DRAM (eDRAM), which is completely compatible with CMOS logic process, to improve circuit implementation efficiency of memory-hungry signal processing algorithms. In spite of its apparent cell area efficiency advantage over SRAM, planar eDRAM is not being widely used in practice, mainly due to its very short retention time (e.g., few $\upmu $ s and even a few hundreds ns). In this work, we contend that short retention time may not necessarily be a fundamental issue for implementing signal processing algorithms because they typically handle streaming data, which exhibits regular and predictable data access patterns, and has a large algorithm/architecture design space. This study elaborates on the rationale and application of using a planar eDRAM in memory-hungry signal processing circuit implementations, and discusses the possible algorithm and architecture design strategies to better embrace the use of planar eDRAM. For the purpose of demonstration, we use low-density parity-check (LDPC) code decoding and motion estimation in video encoding as test vehicles. Beyond a straightforward SRAM replacement, we propose an interleaved read/write page-mode DRAM operation to reduce planar eDRAM energy consumption by leveraging LDPC code decoding data access pattern, and we investigate the potential of using planar eDRAM to enable a higher degree of image data reuse in motion estimation by proposing a folded scan structure to further improve its effectiveness. We carried out detailed planar eDRAM SPICE simulations at 45 nm node to obtain its characteristics, based on which we quantitatively evaluate the effectiveness of using planar eDRAM in these two case studies.

Low Power Decoding of LDPC Codes

Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

Iterative Linear Programming Decoding of Nonbinary LDPC Codes With Linear Complexity

The problem of low-complexity linear programming (LP) decoding of nonbinary low-density parity-check (LDPC) codes is considered, and an iterative LP decoding algorithm is presented. Results that were previously derived for binary LDPC codes are extended to the nonbinary case. Both simple and generalized nonbinary LDPC codes are considered. It is shown how the algorithm can be implemented efficiently using a finite-field fast Fourier transform. Then, the convergence rate of the algorithm is analyzed. The complexity of the algorithm scales linearly in the block length, and it can approximate, up to an arbitrarily small relative error, the objective function of the exact LP solution. When applied to a typical code from an appropriate nonbinary LDPC code ensemble, the algorithm can correct a constant fraction of errors in linear (in the block length) computational complexity. Computer experiments with the new iterative LP decoding algorithm show that, in the error floor region, it can have better performance compared to belief propagation decoding, with similar computational requirements.

Effects of Single-Cycle Structure on Iterative Decoding of Low-Density Parity-Check Codes

We consider communication over the binary erasure channel (BEC) using low-density parity-check (LDPC) codes and belief propagation (BP) decoding. For fixed numbers of BP iterations, the bit error probability approaches a limit as blocklength tends to infinity, and the limit is obtained via density evolution. On the other hand, the difference between the bit error probability of codes with blocklength $n$ and that in the large blocklength limit is asymptotically $\alpha(\epsilon,t)/n + \Theta(n^{-2})$ where $\alpha(\epsilon,t)$ denotes a specific constant determined by the code ensemble considered, the number $t$ of iterations, and the erasure probability $\epsilon$ of the BEC. In this paper, we derive a set of recursive formulas which allows evaluation of the constant $\alpha(\epsilon,t)$ for standard irregular ensembles. The dominant difference $\alpha(\epsilon,t)/n$ can be considered as effects of cycle-free and single-cycle structures of local graphs. Furthermore, it is confirmed via numerical simulations that estimation of the bit error probability using $\alpha(\epsilon,t)$ is accurate even for small blocklengths.

Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes

We propose a non-binary stochastic decoding algorithm for low-density parity-check (LDPC) codes over GF(q) with degree two variable nodes, called Adaptive Multiset Stochastic Algorithm (AMSA). The algorithm uses multisets, an extension of sets that allows multiple occurrences of an element, to represent probability mass functions that simplifies the structure of the variable nodes. The run-time complexity of one decoding cycle using AMSA is O(q) for conventional memory architectures, and O(1) if a custom memory architecture is used. Two fully-parallel AMSA decoders are implemented on FPGA for two (192,96) (2,4)-regular codes over GF(64) and GF(256), both achieving a maximum clock frequency of 108 MHz. The GF(64) decoder has a coded throughput of 65 Mb/s at Eb/N0=2.4 dB when using conventional memory, while a decoder using the custom memory version can achieve 698 Mb/s at the same Eb/N0. At a frame error rate (FER) of 2×10-6 the GF(64) version of the algorithm is only 0.04 dB away from the floating-point SPA performance, and for the GF(256) code the difference is 0.2 dB. To the best of our knowledge, this is the first fully parallel non-binary LDPC decoder over GF(256) reported in the literature.

AID: An Energy Efficient Decoding Scheme for LDPC Codes in Wireless Body Area Sensor Networks

One of the major challenges in Wireless Body Area Networks (WBANs) is to prolong the lifetime of network. Tra- ditional research work focuses on minimizing transmit power; however, in the case of short range communication the consumption power in decoding is significantly larger than transmit power. This paper investigates the minimization of total power consumption by reducing the decoding power consumption. For achieving a desired Bit Error Rate (BER), we introduce some fundamental results on the basis of iterative message-passing algorithms for Low Density Parity Check Code (LDPC). To reduce energy dissipation in decoder, LDPC based coded communications between sensors are considered. Moreover, we evaluate the performance of LDPC at different code rates and introduce Adaptive Itera- tive Decoding (AID) by exploiting threshold on the number of iterations for a certain BER (10−4). In iterative LDPC decoding, the total energy consumption of network is reduced by 20 - 25%.

Channel Capacity and Soft-Decision Decoding of LDPC Codes for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Spin-torque transfer magnetic random access memory (STT-MRAM) has emerged as a promising non-volatile memory (NVM) technology, featuring compelling advantages in scalability, speed, endurance, and power consumption. In this paper, we focus on large-capacity stand-alone STT-MRAM, and investigate the channel capacity and the viability of applying low-density parity-check (LDPC) codes with soft-decision decoding to correct the memory cell errors and improve the storage density of STT-MRAM. We propose to use LDPC codes with short codeword lengths, with the reliability-based min-sum (RB-MS) algorithm for decoding. Furthermore, we propose to use the capacity-maximization criterion to design the quantizer and minimize the number of quantization bits. Simulation results demonstrate the potential of applying short-block-length LDPC codes with soft-decision decoding to improve the yield and push the scaling limitation of STT-MRAM.

Stochastic Decoding of LDPC Codes over GF(q)

Despite the outstanding performance of non-binary low-density parity-check (LDPC) codes over many communication channels, they are not in widespread use yet. This is due to the high implementation complexity of their decoding algorithms, even those that compromise performance for the sake of simplicity. In this paper, we present three algorithms based on stochastic computation to reduce the decoding complexity. The first is a purely stochastic algorithm with error-correcting performance matching that of the sum-product algorithm (SPA) for LDPC codes over Galois fields with low order and a small variable node degree. We also present a modified version which reduces the number of decoding iterations required while remaining purely stochastic and having a low per-iteration complexity. The second algorithm, relaxed half-stochastic (RHS) decoding, combines elements of the SPA and the stochastic decoder and uses successive relaxation to match the error-correcting performance of the SPA. Furthermore, it uses fewer iterations than the purely stochastic algorithm and does not have limitations on the field order and variable node degree of the codes it can decode. The third algorithm, NoX, is a fully stochastic specialization of RHS for codes with a variable node degree 2 that offers similar performance, but at a significantly lower computational complexity. We study the performance and complexity of the algorithms; noting that all have lower per-iteration complexity than SPA and that RHS can have comparable average per-codeword computational complexity, and NoX a lower one.

A Deviation-Based Conditional Upper Bound on the Error Floor Performance for Min-Sum Decoding of Short LDPC Codes

Conditional upper bounds are given for min-sum decoding of low-density parity-check codes in the error floor region. It is generally thought that absorbing sets, i.e., small collections of variable nodes connected to a relatively small number of unsatisfied check nodes, are the primary source of errors in the error floor region. The conditional upper bounds presented here are based on the assumption that all error floor errors are caused by absorbing sets. In order to bound the probability of error associated with each absorbing set, a directed-edge Tanner graph is used to link absorbing sets to low-weight deviations. These low-weight deviations result when a proportionally large number of nodes within a stopping set belong to an absorbing set contained inside the stopping set. A complete collection of the most problematic absorbing sets, and the minimum deviation weights that result from them, are used to derive a conditional upper bound on the probability of error for min-sum decoding of low-density parity-check codes. Simulation results are given to demonstrate the accuracy of the bound.

Maximum Likelihood Erasure Decoding of LDPC Codes: Pivoting Algorithms and Code Design

This paper investigates efficient maximum-likelihood (ML) decoding of low-density parity-check (LDPC) codes over erasure channels. A set of algorithms, referred to as pivoting algorithms, is developed. The aim is to limit the average number of pivots (or reference variables) from which all the other erased symbols are recovered iteratively. The suggested algorithms exhibit different trade-offs between complexity of the pivoting phase and average number of pivots. Moreover, a systematic procedure to design LDPC code ensembles for efficient ML decoding is proposed. Numerical results illustrate that the designed LDPC codes achieve a near-optimum performance (very close to the Singleton bound, at least down to a codeword error rate level 10-8) with an affordable decoding complexity. For one of the presented codes and algorithms, a software implementation has been developed which is capable to provide data rates above 1.5 Gbps on a commercial computing platform.

Doubly multistage decoding of low-density parity-check codes over ℤ 2 m

A doubly multistage decoder (DMD) for low-density parity-check codes over ℤ2m, m>1, which fuses the multistage decoding approaches of Armand et al. and Varnica et al., is proposed. Two variants of the DMD are considered. The first (respectively, second) performs belief-propagation (BP) [respectively, offset min-sum (OMS)] decoding in each decoding stage and is referred to as DMD - BP (respectively, DMD - OMS). For the moderate-length codes considered in this study, the computer simulations show the DMD - BP (respectively, DMD - OMS) achieving coding gains of up to 0.43 dB (respectively, 0.67 dB) over standard BP decoding at a bit error rate of 10−6 on an additive-white-Gaussian-noise channel, while requiring significantly less computational power. Remarkably, DMD - OMS outperforms DMD - BP, yet has lower computational complexity than DMD - BP. Snapshots of the log-likelihood ratio densities of the decoded bits midway through the decoding process explain the superiority of the DMD over standard BP decoding.

Different perspective and approach to implement adaptive normalised belief propagation-based decoding for low-density parity check codes

In this study, the authors propose an improved version of the min-sum algorithm for low-density parity check code decoding, which the authors call ‘adaptive normalised BP-based’ algorithm. Their decoder provides a compromise solution between belief propagation and the min-sum algorithms by adding an exponent offset to each variable node's intrinsic information in the check node update equation. The extrinsic information from the min-sum decoder is then adjusted by applying a negative power of the two scale factor, which can be easily implemented by right shifting the min-sum extrinsic information. The difference between their approach and other adaptive normalised min-sum decoders is that the authors select the normalisation scale factor using a clear analytical approach based on the underlying principles. The simulation results show that the proposed decoder outperforms the min-sum decoder and performs very close to the BP decoder with lower complexity.

Verification Decoding of High-Rate LDPC Codes With Applications in Compressed Sensing

This paper considers the performance of (j, k)-regular low-density parity-check (LDPC) codes with message-passing (MP) decoding algorithms in the high-rate regime. In particular, we derive the high-rate scaling law for MP decoding of LDPC codes on the binary erasure channel (BEC) and the q-ary symmetric channel (q-SC). For the BEC and a fixed j, the density evolution (DE) threshold of iterative decoding scales like Θ(k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) and the critical stopping ratio scales like Θ(k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-j/(j-2)</sup> ). For the q-SC and a fixed j, the DE threshold of verification decoding depends on the details of the decoder and scales like Θ(k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) for one decoder. Using the fact that coding over large finite alphabets is very similar to coding over the real numbers, the analysis of verification decoding is also extended to the compressed sensing (CS) of strictly sparse signals. A DE-based approach is used to analyze the CS systems with randomized-reconstruction guarantees. This leads to the result that strictly sparse signals can be reconstructed efficiently with high probability using a constant oversampling ratio (i.e., when the number of measurements scales linearly with the sparsity of the signal). A stopping-set-based approach is also used to get stronger (e.g., uniform-in-probability) reconstruction guarantees.

On Combining Chase-2 and Sum-Product Algorithms for LDPC Codes

This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.